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1. 发明申请

US20150194417A1 Snapback Inhibiting Clamp Circuitry For Mosfet ESD Protection Circuits 审中-公开
标题翻译：用于Mosfet ESD保护电路的Snapback抑制钳位电路
公开(公告)号：US20150194417A1
公开(公告)日：2015-07-09
申请号：US14149112
申请日：2014-01-07
申请人： Silicon Laboratories Inc.
发明人： Jeremy C. Smith
IPC分类号： H01L27/02
CPC分类号： H01L27/0266 , H02H9/046
摘要： Circuit configurations and related methods are disclosed that may be implemented to protect circuitry from adverse effects of transistor snapback that may occur during ESD events. The circuitry and methods may be implemented as part of distributed ESD rail clamping circuitry that includes ESD circuit elements that are coupled to power nodes or supply rails and not to signal nodes or signal pads of the circuitry in a manner that reduces parasitic loading on signal pads to reduce or substantially eliminate NMOS and/or PMOS transistor snapback occurrence, while at the same time providing rail-clamping capability during occurrence of ESD events. Using the disclosed circuitry and methods, at least a portion of ESD current may be diverted by clamp circuitry from or to a supply rail to reduce voltage differential across the sources of CMOS output transistors relative to their bulk terminals in a manner that reduces forward biasing of parasitic BJTs present at each of the CMOS output transistors, thus reducing or substantially eliminating occurrence of transistor snapback during an ESD event.
摘要翻译：公开了可以实现的电路配置和相关方法，以保护电路免受可能在ESD事件期间发生的晶体管快速恢复的不利影响。电路和方法可以被实现为分布式ESD轨道钳位电路的一部分，其包括耦合到功率节点或电源轨的ESD电路元件，而不是以减少信号焊盘上的寄生负载的方式向电路的信号节点或信号焊盘发信号以减少或基本上消除NMOS和/或PMOS晶体管突发发生，同时在ESD事件发生期间提供轨道钳位能力。使用所公开的电路和方法，ESD电流的至少一部分可以由钳位电路从电源轨转移到供电轨，以减少CMOS输出晶体管源相对于它们的体端子的电压差，以减少正向偏置存在于每个CMOS输出晶体管的寄生BJT，从而减少或基本上消除在ESD事件期间发生晶体管快速恢复。

2. 发明申请

US20170194788A1 DYNAMIC TRIGGER VOLTAGE CONTROL FOR AN ESD PROTECTION DEVICE 审中-公开
公开(公告)号：US20170194788A1
公开(公告)日：2017-07-06
申请号：US14984929
申请日：2015-12-30
申请人： Silicon Laboratories Inc.
发明人： Jeremy C. Smith
IPC分类号： H02H9/04 , H01L29/739 , H01L27/02
CPC分类号： H02H9/046 , H01L27/0259 , H01L27/0262 , H01L27/0266 , H01L27/0292 , H01L29/7393 , H01L29/7394 , H02H9/044
摘要： Circuit configurations and related methods are provided that may be implemented using insulated-gate bipolar transistor (IGBT) device circuitry to protect at risk circuitry (e.g., such as high voltage output buffer circuitry or any other circuitry subject to undesirable ESD events) from damage due to ESD events that may occur during system assembly. The magnitude of the trigger voltage VT1 threshold for an IGBT ESD protection device may be dynamically controlled between at least two different values so that trigger voltage VT1 threshold for an IGBT ESD protection device may be selectively reduced when needed to better enable ESD operation.

3. 发明申请

US20150228638A1 Diode Circuit Layout Topology With Reduced Lateral Parasitic Bipolar Action 有权
标题翻译：具有减少侧向寄生双极性作用的二极管电路布局拓扑
公开(公告)号：US20150228638A1
公开(公告)日：2015-08-13
申请号：US14177670
申请日：2014-02-11
申请人： Silicon Laboratories Inc.
发明人： Jeremy C. Smith , Anirudh Oberoi , William Moore , Michael Khazhinsky
IPC分类号： H01L27/02 , H01L29/06 , H01L29/861
CPC分类号： H01L27/0248 , H01L27/0255 , H01L29/0649 , H01L29/8613
摘要： Diode circuit layout topologies and methods are disclosed that exhibit reduced lateral parasitic bipolar characteristics at lateral parasitic bipolar circuit emitter edges during ESD or other voltage events as compared to conventional circuit layout topologies. The disclosed diode circuit layout topologies may be implemented to recess parasitic emitter ends relative to surrounding well ties, for example, to reduce or substantially eliminate parasitic bipolar action at lateral emitter edges of the circuitry during ESD events so as to provide higher current threshold for device failure, allowing for smaller device area and/or improved ESD robustness for a given circuit device.
摘要翻译：公开了二极管电路布局拓扑和方法，其在ESD或其它电压事件期间在横向寄生双极电路发射极边缘处表现出减小的横向寄生双极特性，与常规电路布局拓扑相比。所公开的二极管电路布局拓扑结构可被实现为相对于周围的连接环凹陷寄生发射极端，例如以减少或基本消除在ESD事件期间在电路的横向发射极边缘处的寄生双极作用，从而为器件提供更高的电流阈值故障，允许给定电路设备的较小的设备面积和/或改善的ESD稳健性。

4. 发明申请

US20200169079A1 High-Voltage Tolerant Bi-Directional Electrostatic Discharge Protection Circuit 审中-公开
公开(公告)号：US20200169079A1
公开(公告)日：2020-05-28
申请号：US16199609
申请日：2018-11-26
申请人： Silicon Laboratories Inc.
发明人： Jeremy C. Smith
IPC分类号： H02H9/04 , H01L27/02 , H01L29/739
摘要： In an embodiment, an apparatus includes: a signal pad; a first diode having a first terminal coupled to the signal pad and a second terminal, the first diode having a first polarity; a second diode having a second terminal coupled to the signal pad and a first terminal, the second diode having a second polarity; a first insulated gate bipolar transistor (IGBT) having a first polarity, the first IGBT coupled between the second terminal of the first diode and a reference voltage node; and a second IGBT having the first polarity, the second IGBT coupled between the first terminal of the second diode and the reference voltage node.

5. 发明授权

US10063048B2 Dynamic trigger voltage control for an ESD protection device 有权
公开(公告)号：US10063048B2
公开(公告)日：2018-08-28
申请号：US14984929
申请日：2015-12-30
申请人： Silicon Laboratories Inc.
发明人： Jeremy C. Smith
IPC分类号： H02H9/04 , H01L27/02 , H01L29/739
CPC分类号： H02H9/046 , H01L27/0259 , H01L27/0262 , H01L27/0266 , H01L27/0292 , H01L29/7393 , H01L29/7394 , H02H9/044
摘要： Circuit configurations and related methods are provided that may be implemented using insulated-gate bipolar transistor (IGBT) device circuitry to protect at risk circuitry (e.g., such as high voltage output buffer circuitry or any other circuitry subject to undesirable ESD events) from damage due to ESD events that may occur during system assembly. The magnitude of the trigger voltage VT1 threshold for an IGBT ESD protection device may be dynamically controlled between at least two different values so that trigger voltage VT1 threshold for an IGBT ESD protection device may be selectively reduced when needed to better enable ESD operation.

6. 发明授权

US09324701B2 Diode circuit layout topology with reduced lateral parasitic bipolar action 有权
标题翻译：二极管电路布局拓扑结构具有减少的侧向寄生双极作用
公开(公告)号：US09324701B2
公开(公告)日：2016-04-26
申请号：US14177670
申请日：2014-02-11
申请人： Silicon Laboratories Inc.
发明人： Jeremy C. Smith , Anirudh Oberoi , William Moore , Michael Khazhinsky
IPC分类号： H01L29/47 , H01L27/02 , H01L29/861 , H01L29/06
CPC分类号： H01L27/0248 , H01L27/0255 , H01L29/0649 , H01L29/8613
摘要： Diode circuit layout topologies and methods are disclosed that exhibit reduced lateral parasitic bipolar characteristics at lateral parasitic bipolar circuit emitter edges during ESD or other voltage events as compared to conventional circuit layout topologies. The disclosed diode circuit layout topologies may be implemented to recess parasitic emitter ends relative to surrounding well ties, for example, to reduce or substantially eliminate parasitic bipolar action at lateral emitter edges of the circuitry during ESD events so as to provide higher current threshold for device failure, allowing for smaller device area and/or improved ESD robustness for a given circuit device.
摘要翻译：公开了二极管电路布局拓扑和方法，其在ESD或其它电压事件期间在横向寄生双极电路发射极边缘处表现出减小的横向寄生双极特性，与常规电路布局拓扑相比。所公开的二极管电路布局拓扑结构可被实现为相对于周围的连接环凹陷寄生发射极端，例如以减少或基本消除在ESD事件期间在电路的横向发射极边缘处的寄生双极作用，从而为器件提供更高的电流阈值故障，允许给定电路设备的较小的设备面积和/或改善的ESD稳健性。

7. 发明授权

US11031778B2 High-voltage tolerant bi-directional electrostatic discharge protection circuit 有权
公开(公告)号：US11031778B2
公开(公告)日：2021-06-08
申请号：US16199609
申请日：2018-11-26
申请人： Silicon Laboratories Inc.
发明人： Jeremy C. Smith
IPC分类号： H02H9/04 , H01L27/02 , H01L29/739
摘要： In an embodiment, an apparatus includes: a signal pad; a first diode having a first terminal coupled to the signal pad and a second terminal, the first diode having a first polarity; a second diode having a second terminal coupled to the signal pad and a first terminal, the second diode having a second polarity; a first insulated gate bipolar transistor (IGBT) having a first polarity, the first IGBT coupled between the second terminal of the first diode and a reference voltage node; and a second IGBT having the first polarity, the second IGBT coupled between the first terminal of the second diode and the reference voltage node.

8. 发明授权

US10249611B1 Diode string configured with guard ring silicon-controlled rectifier for negative electrostatic discharge protection 有权
公开(公告)号：US10249611B1
公开(公告)日：2019-04-02
申请号：US15964260
申请日：2018-04-27
申请人： Silicon Laboratories Inc.
发明人： Yunfeng Xi , Jeremy C. Smith
IPC分类号： H01L27/02 , H01L29/06
摘要： A diode string for a semiconductor circuit configured with a guard ring silicon-controlled rectifier (SCR) for electrostatic discharge (ESD) protection. The diode string includes multiple NPN transistor diode structures formed in an N-well structure and electrically coupled in series between a reference voltage node and an I/O pad. Each diode structure may include a P-type retro-well structure including at least one N+ doped region and at least one P+ doped region. The P+ guard ring includes at least one P+ doped structure formed in the N-well structure disposed on either side of the first diode structure and electrically coupled to the reference voltage node. The P+ guard ring forms the SCR with the first diode structure. The diode string is triggered in response to an ESD event, which activates the SCR, and the SCR clamps the I/O pad to the reference voltage node and handles the ESD current.

9. 发明授权

US09502399B1 Diode string circuit configurations with improved parasitic silicon-controlled rectifier (SCR) conduction during electrostatic discharge (ESD) events 有权
标题翻译：具有改善的静电放电（ESD）事件中的寄生硅控整流器（SCR）导通的二极管串电路配置
公开(公告)号：US09502399B1
公开(公告)日：2016-11-22
申请号：US14752236
申请日：2015-06-26
申请人： Silicon Laboratories Inc.
发明人： Jeremy C. Smith , Anirudh Oberoi
IPC分类号： H01L29/66 , H01L27/02 , H01L29/87 , H01L29/735 , H01L29/732
CPC分类号： H01L27/0262 , H01L27/0255 , H01L29/732 , H01L29/735
摘要： Diode string configurations are provided that employ one or more guard bars (GBARS) positioned adjacent an end diode structure of a diode string to create a parasitic silicon-controlled rectifier (SCR) coupling between the end diode structure and the guard bar/s that operates to discharge current of an ESD event through a lateral parasitic bipolar transistor of the SCR and away from the individual diodes of the diode string. One or more of the disclosed guard bars may be positioned adjacent to a diode on a first end of a diode string to create a lateral SCR coupling for ESD discharge away from all of the diodes in the diode string without requiring positioning of a last diode on an opposite end of the same diode string adjacent the first terminal diode.
摘要翻译：提供二极管串配置，其采用位于二极管串的端部二极管结构附近的一个或多个保护条（GBARS），以产生在端部二极管结构和操作的保护条之间耦合的寄生硅可控整流器（SCR）以通过SCR的侧向寄生双极晶体管和远离二极管串的各个二极管来放电ESD事件的电流。所公开的保护条中的一个或多个可以与二极管串的第一端上的二极管相邻，以产生用于ESD放电的横向SCR耦合，远离二极管串中的所有二极管，而不需要最后一个二极管的定位与第一端子二极管相邻的相同二极管串的相对端。

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