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    • 1. 发明授权
    • Data speculation for array processors
    • 阵列处理器的数据推测
    • US09418043B2
    • 2016-08-16
    • US14385953
    • 2014-03-07
    • Sony Corporation
    • Jim RasmussonHåkan JonssonJonas GustavssonAnders Isberg
    • G06F9/30G06F15/80G06F9/38
    • G06F15/80G06F9/3832G06F9/3887
    • A method is disclosed of utilizing a plurality of Arithmetic Logic Units (ALUs) of an array processor. It is determined that a first quantity of the ALUs are scheduled to execute a function during a given processing cycle, with each ALU being scheduled to use a respective one of a plurality of selected input vectors as an input. It is also determined that a second quantity of the ALUs are not scheduled for use during the given processing cycle. A plurality of predicted future input vectors that differ from the plurality of selected input vectors are determined. The second quantity of ALUs are scheduled to execute the function during the given processing cycle using respective ones of the plurality of predicted future input vectors as inputs. After completion of the processing cycle, function outputs received from the first and second quantity of ALUs are cached.
    • 公开了利用阵列处理器的多个算术逻辑单元(ALU)的方法。 确定第一数量的ALU被调度为在给定处理周期期间执行功能,其中每个ALU被调度为使用多个选择的输入向量中的相应一个作为输入。 还确定在给定处理周期期间第二数量的ALU不被安排用于使用。 确定与多个选择的输入向量不同的多个预测未来输入向量。 第二数量的ALU被调度为在给定处理周期期间使用多个预测未来输入向量中的相应的输入向量来执行该功能作为输入。 在处理周期完成之后,从第一和第二数量的ALU接收的功能输出被缓存。
    • 6. 发明申请
    • Data Speculation for Array Processors
    • 阵列处理器的数据推测
    • US20150363356A1
    • 2015-12-17
    • US14385953
    • 2014-03-07
    • Sony Corporation
    • Jim RasmussonHåkan JonssonJonas GustavssonAnders Isberg
    • G06F15/80
    • G06F15/80G06F9/3832G06F9/3887
    • A method is disclosed of utilizing a plurality of Arithmetic Logic Units (ALUs) of an array processor. It is determined that a first quantity of the ALUs are scheduled to execute a function during a given processing cycle, with each ALU being scheduled to use a respective one of a plurality of selected input vectors as an input. It is also determined that a second quantity of the ALUs are not scheduled for use during the given processing cycle. A plurality of predicted future input vectors that differ from the plurality of selected input vectors are determined. The second quantity of ALUs are scheduled to execute the function during the given processing cycle using respective ones of the plurality of predicted future input vectors as inputs. After completion of the processing cycle, function outputs received from the first and second quantity of ALUs are cached.
    • 公开了利用阵列处理器的多个算术逻辑单元(ALU)的方法。 确定第一数量的ALU被调度为在给定处理周期期间执行功能,其中每个ALU被调度为使用多个选择的输入向量中的相应一个作为输入。 还确定在给定处理周期期间第二数量的ALU不被安排用于使用。 确定与多个选择的输入向量不同的多个预测未来输入向量。 第二数量的ALU被调度为在给定处理周期期间使用多个预测未来输入向量中的相应的输入向量来执行该功能作为输入。 在处理周期完成后,从第一和第二数量的ALU接收的功能输出被缓存。