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1. 发明授权

US09361952B2 Storage controlling apparatus, memory system, information processing system and storage controlling method 有权
标题翻译：存储控制装置，存储系统，信息处理系统和存储控制方法
公开(公告)号：US09361952B2
公开(公告)日：2016-06-07
申请号：US13780655
申请日：2013-02-28
申请人： Sony Corporation
发明人： Kenichi Nakanishi , Keiichi Tsutsui , Yasushi Fujinami , Naohiro Adachi , Hideaki Okubo , Ken Ishii , Tatsuo Shinbashi
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/00 , G11C7/1006
摘要： Disclosed herein is a storage controlling apparatus including: a decision portion configured to decide whether or not a bit number of a specific value from between binary values is greater than a reference value in at least part of input data to a memory cell, which executes rewriting to one of the binary values and rewriting to the other one of the binary values in order in a writing process, to generate decision data indicative of a result of the decision; and a write side outputting portion configured to output, when it is decided that the bit number is greater than the reference value, the input data at least part of which is inverted as write data to the memory cell together with the decision data.
摘要翻译：这里公开了一种存储控制装置，包括：判定部，被配置为判定在二进制值之间的特定值的位数是否大于至少部分输入数据的参考值，该存储单元执行重写到二进制值中的一个并且在写入过程中按顺序重写到另一个二进制值，以产生指示决定结果的决定数据; 以及写入侧输出部分，被配置为当确定所述位数大于所述参考值时，输出至少部分所述输入数据与所述决定数据一起作为写入数据被反转为所述存储器单元。

2. 发明授权

US09280455B2 Memory control device, non-volatile memory, and memory control method 有权
标题翻译：存储器控制器，非易失性存储器和存储器控制方法
公开(公告)号：US09280455B2
公开(公告)日：2016-03-08
申请号：US13945987
申请日：2013-07-19
申请人： Sony Corporation
发明人： Naohiro Adachi , Keiichi Tsutsui , Ken Ishii , Hideaki Okubo , Kenichi Nakanishi , Yasushi Fujinami , Tatsuo Shinbashi , Lui Sakai , Ryoji Ikegaya
IPC分类号： G06F12/02 , G06F12/00 , G11C13/00
CPC分类号： G06F12/00 , G11C13/0002 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2213/78
摘要： Provided is a memory control device, including a write control unit that sequentially designates a memory block, a write processing unit that writes write data in the designated memory block, a verifying unit that reads read data from the memory block and verifies whether or not the read data matches the write data for each of a plurality of memory cells, a retry inhibiting unit that inhibits a retry process from being performed in a memory cell in which the read data matches the write data among the plurality of memory cells, and a retry control unit that designates at least some memory blocks among the plurality of memory blocks and simultaneously executes the retry process when the read data does not match the write data in any one of the plurality of memory cells in which all the write data is written.
摘要翻译：提供了一种存储器控制装置，包括顺序地指定存储块的写入控制单元，将写入数据写入指定的存储器块的写入处理单元，从存储器块读取读取的数据并验证是否读取数据与多个存储器单元中的每一个的写入数据相匹配，重试禁止单元禁止在读取数据与多个存储器单元中的写入数据匹配的存储器单元中进行重试处理，并且重试控制单元，其指定所述多个存储器块中的至少一些存储块，并且当读取数据与写入所有写入数据的所述多个存储器单元中的任何一个存储器单元中的写入数据不匹配时，同时执行重试处理。

3. 发明申请

US20140059404A1 MEMORY CONTROL DEVICE, MEMORY DEVICE, INFORMATION PROCESSING SYSTEM AND MEMORY CONTROL METHOD 审中-公开
标题翻译：存储控制装置，存储装置，信息处理系统和存储器控制方法
公开(公告)号：US20140059404A1
公开(公告)日：2014-02-27
申请号：US13953960
申请日：2013-07-30
申请人： Sony Corporation
发明人： Hideaki Okubo , Keiichi Tsutsui , Yasushi Fujinami , Kenichi Nakanishi , Naohiro Adachi , Ken Ishii , Tatsuo Shinbashi
IPC分类号： G06F11/10 , G06F12/08
CPC分类号： G06F11/1016 , G06F11/1068 , G06F12/08 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2029/0411
摘要： There is provided a memory control device, including a request determining unit that determines a type of a request, and a control unit that writes read data read from a memory cell array in the memory cell array in units of predetermined pages of the memory cell array when the request is a refresh request, and divides the page of write data into units of groups and writes the page of the write data in the memory cell array over twice or more when the request is a write request.
摘要翻译：提供了一种存储器控制装置，包括确定请求的类型的请求确定单元，以及以存储单元阵列的预定页为单位将从存储单元阵列读出的读取数据写入存储单元阵列的控制单元当请求是刷新请求时，并且当请求是写入请求时，将写入数据的页面划分成组的单元并将写入数据的页面写入存储单元阵列中两次或更多次。

4. 发明申请

US20130272078A1 STORAGE CONTROLLING APPARATUS, MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM AND STORAGE CONTROLLING METHOD 有权
标题翻译：存储控制设备，存储系统，信息处理系统和存储控制方法
公开(公告)号：US20130272078A1
公开(公告)日：2013-10-17
申请号：US13780655
申请日：2013-02-28
申请人： SONY CORPORATION
发明人： Kenichi Nakanishi , Keiichi Tsutsui , Yasushi Fujinami , Naohiro Adachi , Hideaki Okubo , Ken Ishii , Tatsuo Shinbashi
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/1006
摘要： Disclosed herein is a storage controlling apparatus including: a decision portion configured to decide whether or not a bit number of a specific value from between binary values is greater than a reference value in at least part of input data to a memory cell, which executes rewriting to one of the binary values and rewriting to the other one of the binary values in order in a writing process, to generate decision data indicative of a result of the decision; and a write side outputting portion configured to output, when it is decided that the bit number is greater than the reference value, the input data at least part of which is inverted as write data to the memory cell together with the decision data.
摘要翻译：这里公开了一种存储控制装置，包括：判定部，被配置为判定在二进制值之间的特定值的位数是否大于至少部分输入数据的参考值，该存储单元执行重写到二进制值中的一个并且在写入过程中按顺序重写到另一个二进制值，以产生指示决定结果的决定数据; 以及写入侧输出部分，被配置为当确定所述位数大于所述参考值时，输出至少部分所述输入数据与所述决定数据一起作为写入数据被反转为所述存储器单元。

5. 发明授权

US11562197B2 Non-contact communication medium and recording medium cartridge 有权
公开(公告)号：US11562197B2
公开(公告)日：2023-01-24
申请号：US17046071
申请日：2019-03-28
申请人： SONY CORPORATION
发明人： Hiroaki Nakano , Eiji Nakashio , Kazuo Anno , Takanobu Iwama , Shinya Tochikubo , Naohiro Adachi , Masayoshi Abe , Uichiro Omae
IPC分类号： G11B23/04 , G06K19/077 , G11B23/107
摘要： A non-contact communication medium according to an embodiment of the present technology is a non-contact communication medium for a recording medium cartridge, including: a circuit component; a support substrate; and an antenna coil. The circuit component has a memory unit capable of storing management information relating to the recording medium cartridge therein. The support substrate supports the circuit component. The antenna coil includes a coil unit that is electrically connected to the circuit component and formed on the support substrate, an inductance value of the coil unit being 0.3 μH or more and 2.0 μH or less.

6. 发明授权

US11145329B2 Recording medium cartridge and drive device 有权
公开(公告)号：US11145329B2
公开(公告)日：2021-10-12
申请号：US17053573
申请日：2019-03-08
申请人： Sony Corporation
发明人： Kazuo Anno , Eiji Nakashio , Takanobu Iwama , Naohiro Adachi , Shinya Tochikubo , Masayoshi Abe
IPC分类号： G11B23/02 , G06K19/04 , G11B5/78 , G11B5/008
摘要： A recording medium cartridge according to an embodiment of the present technology includes: an information recording medium; a first cartridge memory; and a second cartridge memory. The first cartridge memory is capable of storing first information relating to the information recording medium, and includes a non-contact communication medium capable of reading/writing the first information via a first communication device disposed in a drive device. The second cartridge memory is capable of storing second information relating to the information recording medium, and is configured to be capable of reading the second information via a second communication device.

7. 发明授权

US09483425B2 Memory including a band width conversion unit, memory system and memory control method using the same 有权
标题翻译：存储器包括带宽转换单元，存储器系统和使用其的存储器控制方法
公开(公告)号：US09483425B2
公开(公告)日：2016-11-01
申请号：US14459966
申请日：2014-08-14
申请人： Sony Corporation
发明人： Haruhiko Terada , Lui Sakai , Naohiro Adachi
IPC分类号： G06F13/12 , G06F13/16 , G06F13/28
CPC分类号： G06F13/1678 , G06F13/16 , G06F13/1668 , G06F13/1673 , G06F13/28 , G06F13/287
摘要： A memory includes a buffer which retains data, a band conversion unit converts a band of an internal data bus that is used for data transfer between the band conversion unit and the buffer which retains data into a band wider than that of an external data bus that is used for data transfer between the band conversion unit and a memory controller, and an access control unit controls access to a memory cell using the buffer, during a wait time occurring in the internal data bus due to a difference between the band of the internal data bus and the band of the external data bus.
摘要翻译：存储器包括保留数据的缓冲器，频带转换单元将用于频带转换单元和保持数据的缓冲器之间用于数据传输的内部数据总线的频带转换成比外部数据总线宽的频带用于在频带转换单元和存储器控制器之间的数据传输，并且访问控制单元在内部数据总线中发生的等待时间期间由于内部频带之间的差异来控制对使用缓冲器的存储单元的访问数据总线和外部数据总线的频带。

8. 发明授权

US08898541B2 Storage controller, storage device, information processing system, and storage controlling method 有权
标题翻译：存储控制器，存储设备，信息处理系统和存储控制方法
公开(公告)号：US08898541B2
公开(公告)日：2014-11-25
申请号：US13675768
申请日：2012-11-13
申请人： Sony Corporation
发明人： Hideaki Okubo , Keiichi Tsutsui , Kenichi Nakanishi , Yasushi Fujinami , Makiko Yamamoto , Naohiro Adachi
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： A storage controller includes an error correcting code managing portion, an address managing portion and an error correcting portion. The error correcting code managing portion manages a correspondence relationship between predetermined plural pieces of unit data, and a second error code corresponding to the plural pieces of unit data every entry when plural pieces of unit data and a second error correcting code are stored in a storage portion. The address managing portion manages a correspondence relationship between logical addresses and the entries in the error correcting code managing portion. The error correcting portion acquires the entry in the error correction managing portion corresponding to the logical address as an object of read from the address managing portion, and carries out error correction based on the plural pieces of unit data managed in the entry concerned, and the second error correcting code.
摘要翻译：存储控制器包括纠错码管理部分，地址管理部分和纠错部分。当多个单位数据和第二纠错码存储在存储器中时，纠错码管理部分管理预定的多个单位数据与每个条目对应的多个单位数据的第二错误代码的对应关系一部分。地址管理部分管理逻辑地址与纠错码管理部分中的条目之间的对应关系。纠错部从地址管理部获取与作为读取对象的逻辑地址相对应的纠错管理部中的条目，并根据在该条目中管理的多个单位数据进行纠错，第二个纠错码。

9. 发明申请

US20140129904A1 ERROR DETECTION AND CORRECTION APPARATUS, MISMATCH DETECTION APPARATUS, MEMORY SYSTEM AND ERROR DETECTION AND CORRECTION METHOD 有权
标题翻译：错误检测和校正装置，误码检测装置，存储器系统和错误检测和校正方法
公开(公告)号：US20140129904A1
公开(公告)日：2014-05-08
申请号：US14049248
申请日：2013-10-09
申请人： SONY CORPORATION
发明人： Lui Sakai , Yasushi Fujinami , Naohiro Adachi , Keiichi Tsutsui , Tatsuo Shinbashi , Ryoji Ikegaya
IPC分类号： G06F11/10
CPC分类号： G06F11/1012 , H03M13/1515 , H03M13/152 , H03M13/373 , H03M13/6306
摘要： An error detection and correction apparatus includes a code word read-out unit to execute read processing to read out a code word including a plurality of code elements by detection of an erasure position as read data from a memory address and to execute re-read processing to read out the code word as re-read data from the memory address after a predetermined time is elapsed from the time to read out the read data; a timing control erasure position detection unit to detect a position of the code element having a value not matched as the erasure position in the code word by determining whether or not the value is matched per the code word in the read data and the re-read data; and an error correction unit to correct an error based on the erasure position in the code word where the erasure position is detected.
摘要翻译：错误检测和校正装置包括：码字读出单元，用于执行读取处理，以通过从存储器地址检测作为读取数据的擦除位置读出包括多个代码元素的代码字，并执行重新读取处理在从读出数据的时间经过预定时间之后，将代码字读出为来自存储器地址的重新读取数据; 定时控制擦除位置检测单元，通过根据读取的数据中的代码字是否匹配值和重新读取来检测具有与码字中的擦除位置不匹配的值的代码元素的位置数据; 以及错误校正单元，用于基于检测到擦除位置的代码字中的擦除位置校正错误。

10. 发明申请

US20130262737A1 STORAGE CONTROL APPARATUS , STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM AND PROCESSING METHOD 审中-公开
标题翻译：存储控制装置，存储装置，信息处理系统和处理方法
公开(公告)号：US20130262737A1
公开(公告)日：2013-10-03
申请号：US13781260
申请日：2013-02-28
申请人： SONY CORPORATION
发明人： Kenichi Nakanishi , Keiichi Tsutsui , Yasushi Fujinami , Naohiro Adachi , Ken Ishii , Hideaki Okubo , Tatsuo Shinbashi
IPC分类号： G06F12/06
CPC分类号： G06F12/0623 , G06F12/06 , G06F12/0607
摘要： Disclosed herein is a storage control apparatus including: a command processing section configured to receive a command requesting accesses to a plurality of access units by specifying an address in a memory space including a plurality of banks; and an address generating section configured to generate an address of an access unit serving as an object of the accesses in a bank selected from the banks as a bank determined in advance for the specified address.
摘要翻译：这里公开了一种存储控制装置，包括：命令处理部，被配置为通过在包括多个存储体的存储空间中指定地址来接收请求对多个访问单元的访问的命令; 以及地址生成部，被配置为生成作为从所述存储体中选择的存储体中的访问对象的访问单元的地址作为对于所述指定地址预先确定的存储体。

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