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1. 发明授权

US08929488B2 Technique for processing encoded information in a wireless communication network 有权
标题翻译：用于在无线通信网络中处理编码信息的技术
公开(公告)号：US08929488B2
公开(公告)日：2015-01-06
申请号：US13695982
申请日：2010-05-06
申请人： Stefan Müller-Weinfurtner , Toni Brkic , Udo Wachsmann
发明人： Stefan Müller-Weinfurtner , Toni Brkic , Udo Wachsmann
IPC分类号： H04L27/06 , H04L1/00 , H03M13/29 , H03M13/37 , H03M13/41 , H03M13/00 , H03M13/09 , H03M13/23
CPC分类号： H04L1/0054 , H03M13/09 , H03M13/23 , H03M13/2933 , H03M13/3738 , H03M13/413 , H03M13/4169 , H03M13/6525
摘要： A technique for processing information in a wireless communication network is described. In a method in accordance with the technique, a signal encoded with a convolution code is received. The encoded signal comprises information and a check value. The encoded signal is decoded using a Viterbi algorithm to derive the information and the check value. The decoding includes computing a Viterbi state metric. A reliability parameter is then determined based on the Viterbi state metric. The information is selectively processed depending on both the check value and the reliability parameter.
摘要翻译：描述了一种在无线通信网络中处理信息的技术。在根据该技术的方法中，接收利用卷积码编码的信号。编码信号包括信息和检查值。使用维特比算法对编码信号进行解码以导出信息和检查值。解码包括计算维特比状态度量。然后，基于维特比状态度量来确定可靠性参数。根据检查值和可靠性参数，选择性地处理信息。

2. 发明申请

US20130107993A1 Technique for Processing Encoded Information in a Wireless Communication Network 有权
标题翻译：在无线通信网络中处理编码信息的技术
公开(公告)号：US20130107993A1
公开(公告)日：2013-05-02
申请号：US13695982
申请日：2010-05-06
申请人： Stefan Müller-Weinfurtner , Toni Brkic , Udo Wachsmann
发明人： Stefan Müller-Weinfurtner , Toni Brkic , Udo Wachsmann
IPC分类号： H04L1/00
CPC分类号： H04L1/0054 , H03M13/09 , H03M13/23 , H03M13/2933 , H03M13/3738 , H03M13/413 , H03M13/4169 , H03M13/6525
摘要： A technique for processing information in a wireless communication network is described. In a method in accordance with the technique, a signal encoded with a convolution code is received. The encoded signal comprises information and a check value. The encoded signal is decoded using a Viterbi algorithm to derive the information and the check value. The decoding includes computing a Viterbi state metric. A reliability parameter is then determined based on the Viterbi state metric. The information is selectively processed depending on both the check value and the reliability parameter.
摘要翻译：描述了一种在无线通信网络中处理信息的技术。在根据该技术的方法中，接收利用卷积码编码的信号。编码信号包括信息和检查值。使用维特比算法对编码信号进行解码以导出信息和检查值。解码包括计算维特比状态度量。然后，基于维特比状态度量来确定可靠性参数。根据检查值和可靠性参数，选择性地处理信息。

3. 发明授权

US07253816B2 Computer graphics acceleration method and apparatus for evaluating whether points are inside a triangle 有权
标题翻译：用于评估点是否在三角形内的计算机图形加速方法和装置
公开(公告)号：US07253816B2
公开(公告)日：2007-08-07
申请号：US10384183
申请日：2003-03-07
申请人： Toni Brkic
发明人： Toni Brkic
IPC分类号： G06T11/20
CPC分类号： G06T11/40
摘要： A computer graphics accelerator apparatus and method determines whether a pixel at predetermined pixel co-ordinates in an area being rasterized is within a triangle defining a sub-area of the area. The coordinate system in relation to which the triangle is defined is translated such that the pixel co-ordinates are disposed at the origin of the coordinate system. Determinants of matrices based on at least two of the coordinate values of at least two of the vertices are calculated and their signs compared. Based on this comparison a determination as to pixel location with respect to the triangle may be made.
摘要翻译：计算机图形加速器装置和方法确定正在被光栅化的区域中的预定像素坐标处的像素是否在限定该区域的子区域的三角形之内。定义三角形相关的坐标系被平移，使得像素坐标设置在坐标系的原点。计算基于至少两个顶点的至少两个坐标值的矩阵的决定因素并比较它们的符号。基于该比较，可以进行关于相对于三角形的像素位置的确定。

4. 发明授权

US09201818B2 Interface module for HW block 有权
标题翻译： HW块接口模块
公开(公告)号：US09201818B2
公开(公告)日：2015-12-01
申请号：US14116604
申请日：2012-05-10
申请人： Magnus Malmberg , Michael Breschel , Toni Brkic , Christel Bergh , Satbinder Singh Ram
发明人： Magnus Malmberg , Michael Breschel , Toni Brkic , Christel Bergh , Satbinder Singh Ram
IPC分类号： G06F3/00 , G06F13/16 , G06F13/38 , G06F13/10
CPC分类号： G06F13/16 , G06F13/102 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： An interface module for a logic circuit block comprising a processing module, the interface module comprising a control interface for communicating one or more control messages; a data interface for accessing a data storage device; an interface logic block; and a core interface to the processing module, the core interface being connected to the interface logic block for communicating signals between the interface logic block and the processing module. The interface logic block is adapted to receive one or more incoming control message via the control interface; process the one or more control messages including accessing a data storage device via the data interface, initiating processing by the processing module via the core interface, receiving one or more signals from the processing module via the core interface; and to output one or more outgoing control message via the control interface.
摘要翻译：一种用于逻辑电路块的接口模块，包括处理模块，所述接口模块包括用于传送一个或多个控制消息的控制接口; 用于访问数据存储设备的数据接口; 接口逻辑块; 以及到处理模块的核心接口，核心接口连接到接口逻辑块，用于在接口逻辑块和处理模块之间传送信号。接口逻辑块适于经由控制接口接收一个或多个输入控制消息; 处理一个或多个控制消息，包括经由数据接口访问数据存储设备，经由核心接口发起处理模块的处理，经由核心接口从处理模块接收一个或多个信号; 并经由控制接口输出一个或多个输出控制消息。

5. 发明申请

US20140201392A1 Interface Module for HW Block 有权
标题翻译： HW块接口模块
公开(公告)号：US20140201392A1
公开(公告)日：2014-07-17
申请号：US14116604
申请日：2012-05-10
申请人： Magnus Malmberg , Michael Breschel , Toni Brkic , Christel Bergh , Satbinder Singh Ram
发明人： Magnus Malmberg , Michael Breschel , Toni Brkic , Christel Bergh , Satbinder Singh Ram
IPC分类号： G06F13/16 , G06F13/10
CPC分类号： G06F13/16 , G06F13/102 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： An interface module for a logic circuit block comprising a processing module, the interface module comprising a control interface for communicating one or more control messages; a data interface for accessing a data storage device; an interface logic block; and a core interface to the processing module, the core interface being connected to the interface logic block for communicating signals between the interface logic block and the processing module. The interface logic block is adapted to receive one or more incoming control message via the control interface; process the one or more control messages including accessing a data storage device via the data interface, initiating processing by the processing module via the core interface, receiving one or more signals from the processing module via the core interface; and to output one or more outgoing control message via the control interface.
摘要翻译：一种用于逻辑电路块的接口模块，包括处理模块，所述接口模块包括用于传送一个或多个控制消息的控制接口; 用于访问数据存储设备的数据接口; 接口逻辑块; 以及到处理模块的核心接口，核心接口连接到接口逻辑块，用于在接口逻辑块和处理模块之间传送信号。接口逻辑块适于经由控制接口接收一个或多个输入控制消息; 处理一个或多个控制消息，包括经由数据接口访问数据存储设备，经由核心接口发起处理模块的处理，经由核心接口从处理模块接收一个或多个信号; 并经由控制接口输出一个或多个输出控制消息。

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