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1. 发明授权

US08274321B2 Fuse circuit and operation method thereof 有权
标题翻译：保险丝电路及其运行方法
公开(公告)号：US08274321B2
公开(公告)日：2012-09-25
申请号：US12956368
申请日：2010-11-30
申请人： Sung-Soo Chi , Ki-Chang Kwean , Woo-Young Lee
发明人： Sung-Soo Chi , Ki-Chang Kwean , Woo-Young Lee
IPC分类号： G11C17/16 , H01H85/00
CPC分类号： G11C29/785
摘要： A fuse circuit includes a control signal generation unit configured to generate a control signal that is enabled after a moment when a power-up signal is enabled, a potential control unit configured to control potentials of both ends of a fuse in response to the control signal, and a fuse output unit configured to be initialized in response to the power-up signal and output a fuse signal in response to whether the fuse is cut or not.
摘要翻译：熔丝电路包括：控制信号生成单元，被配置为产生在上电信号使能之后启用的控制信号;电位控制单元，被配置为响应于控制信号控制熔丝的两端的电位以及保险丝输出单元，其被配置为响应于所述上电信号被初始化，并且响应于所述熔丝是否被切断而输出熔丝信号。

2. 发明授权

US08116146B2 Semiconductor device and method for driving the same 失效
标题翻译：半导体装置及其驱动方法
公开(公告)号：US08116146B2
公开(公告)日：2012-02-14
申请号：US12345692
申请日：2008-12-30
申请人： Sung-Soo Chi
发明人： Sung-Soo Chi
IPC分类号： G11C5/14
CPC分类号： G11C7/12
摘要： A semiconductor device includes an overdriving control circuit configured to generate a first drive signal and a second drive signal in response to an internal signal of an active command mode, an equalizing signal generating unit configured to generate an equalizing signal which is controlled with an overdriving voltage VPP level higher than a normal drive voltage during a first duration of an activation period and with the normal drive voltage VDD during a second duration of the other activation period after the first duration in response to the first drive signal and the second drive signal, and an equalization unit configured to equalize first and second lines in response to the equalizing signal.
摘要翻译：一种半导体装置，包括响应于有效指令模式的内部信号而产生第一驱动信号和第二驱动信号的过驱动控制电路，均衡信号生成单元，其被配置为产生用过驱动电压控制的均衡信号 VPP电平在激活期间的第一持续时间期间高于正常驱动电压，并且在响应于第一驱动信号和第二驱动信号的第一持续时间之后的另一激活周期的第二持续时间期间具有正常驱动电压VDD，以及均衡单元，被配置为响应于均衡信号来均衡第一和第二线。

3. 发明授权

US07920429B2 Semiconductor memory device for reducing power consumption 有权
标题翻译：用于降低功耗的半导体存储器件
公开(公告)号：US07920429B2
公开(公告)日：2011-04-05
申请号：US12003548
申请日：2007-12-28
申请人： Sung-Soo Chi , Jae-Jin Lee
发明人： Sung-Soo Chi , Jae-Jin Lee
IPC分类号： G11C16/06
CPC分类号： G11C11/4085 , G11C8/08
摘要： A semiconductor memory device which includes: a voltage supplying unit for outputting a power source voltage as a driving source signal during a predetermined time, and then outputting a high voltage as the driving source signal in response to a driving control signal activated in response to an address signal; and a word line control unit for activating a word line at a voltage level of the driving source signal in response to the driving control signal.
摘要翻译：一种半导体存储器件，包括：电压提供单元，用于在预定时间期间输出作为驱动源信号的电源电压，然后响应于响应于所述驱动源信号而被激活的驱动控制信号输出高电压作为驱动源信号地址信号以及字线控制单元，用于响应于驱动控制信号而在驱动源信号的电压电平下激活字线。

4. 发明申请

US20090168560A1 CIRCUIT AND METHOD FOR CONTROLLING LOCAL DATA LINE IN SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：用于控制半导体存储器件中的本地数据线的电路和方法
公开(公告)号：US20090168560A1
公开(公告)日：2009-07-02
申请号：US12344062
申请日：2008-12-24
申请人： Sung-Soo Chi
发明人： Sung-Soo Chi
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G11C7/18 , G11C2207/002
摘要： The present invention relates to a semiconductor memory device, and more particularly, to a circuit and method for controlling local data lines, which can reduce loading on local data lines LIO. The circuit and method for controlling local data lines in accordance with the present invention is characterized by having different line loading of local data lines depending on positions of cell mats. In addition, local data lines between arrays are connected by a switch. Accordingly, the switch is turned on/off by address information about cell mat arrays, thereby preventing unnecessary line loading of local data lines to completely remove unnecessary loading. Moreover, the present invention reduces line loading, thereby improving data processing speed.
摘要翻译：本发明涉及一种半导体存储器件，更具体地说，涉及一种用于控制本地数据线的电路和方法，其可以减少对本地数据线LIO的负载。根据本发明的用于控制本地数据线的电路和方法的特征在于根据电池垫的位置具有不同的本地数据线的线路负载。此外，阵列之间的本地数据线通过交换机连接。因此，通过关于单元阵列阵列的地址信息来打开/关闭开关，从而防止本地数据线的不必要的线路加载以完全消除不必要的负载。此外，本发明减少了线路负载，从而提高了数据处理速度。

5. 发明授权

US07495982B2 Internal voltage generator 有权
标题翻译：内部电压发生器
公开(公告)号：US07495982B2
公开(公告)日：2009-02-24
申请号：US11716633
申请日：2007-03-12
申请人： Sung-Soo Chi
发明人： Sung-Soo Chi
IPC分类号： G11C7/00
CPC分类号： G05F1/465 , G11C5/14
摘要： An internal voltage generation device includes a plurality of output nodes; a bit line precharge voltage generation unit for generating a bit line precharge voltage; a first voltage drop unit for transferring the bit line precharge voltage to a first output node after decreasing the bit line precharge voltage by a first voltage drop amount in response to a test mode signal; and a second voltage drop unit for transferring the bit line precharge voltage to a second output node after decreasing the bit line precharge voltage by a second voltage drop amount in response to the test mode signal, wherein the second voltage drop amount is greater than the first voltage drop amount.
摘要翻译：内部电压产生装置包括多个输出节点; 位线预充电电压产生单元，用于产生位线预充电电压; 第一电压降单元，用于响应于测试模式信号，在将位线预充电电压降低第一电压降量之后，将位线预充电电压传送到第一输出节点; 以及第二电压降单元，用于响应于所述测试模式信号而将所述位线预充电电压降低第二电压降量，将所述位线预充电电压传送到第二输出节点，其中所述第二电压降量大于所述第一输出节点电压降量。

6. 发明申请

US20080080264A1 Internal voltage generator 有权
标题翻译：内部电压发生器
公开(公告)号：US20080080264A1
公开(公告)日：2008-04-03
申请号：US11716633
申请日：2007-03-12
申请人： Sung-Soo Chi
发明人： Sung-Soo Chi
IPC分类号： G11C5/14 , G05F1/10
CPC分类号： G05F1/465 , G11C5/14
摘要： An internal voltage generation device includes a plurality of output nodes; a bit line precharge voltage generation unit for generating a bit line precharge voltage; a first voltage drop unit for transferring the bit line precharge voltage to a first output node after decreasing the bit line precharge voltage by a first voltage drop amount in response to a test mode signal; and a second voltage drop unit for transferring the bit line precharge voltage to a second output node after decreasing the bit line precharge voltage by a second voltage drop amount in response to the test mode signal, wherein the second voltage drop amount is greater than the first voltage drop amount.
摘要翻译：内部电压产生装置包括多个输出节点; 位线预充电电压产生单元，用于产生位线预充电电压; 第一电压降单元，用于响应于测试模式信号，在将位线预充电电压降低第一电压降量之后，将位线预充电电压传送到第一输出节点; 以及第二电压降单元，用于响应于所述测试模式信号而将所述位线预充电电压降低第二电压降量，将所述位线预充电电压传送到第二输出节点，其中所述第二电压降量大于所述第一输出节点电压降量。

7. 发明授权

US07965566B2 Circuit and method for controlling local data line in semiconductor memory device 失效
标题翻译：用于控制半导体存储器件中本地数据线的电路和方法
公开(公告)号：US07965566B2
公开(公告)日：2011-06-21
申请号：US12344062
申请日：2008-12-24
申请人： Sung-Soo Chi
发明人： Sung-Soo Chi
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G11C7/18 , G11C2207/002
摘要： The present invention relates to a semiconductor memory device, and more particularly, to a circuit and method for controlling local data lines, which can reduce loading on local data lines LIO. The circuit and method for controlling local data lines in accordance with the present invention is characterized by having different line loading of local data lines depending on positions of cell mats. In addition, local data lines between arrays are connected by a switch. Accordingly, the switch is turned on/off by address information about cell mat arrays, thereby preventing unnecessary line loading of local data lines to completely remove unnecessary loading. Moreover, the present invention reduces line loading, thereby improving data processing speed.
摘要翻译：本发明涉及一种半导体存储器件，更具体地说，涉及一种用于控制本地数据线的电路和方法，其可以减少对本地数据线LIO的负载。根据本发明的用于控制本地数据线的电路和方法的特征在于根据电池垫的位置具有不同的本地数据线的线路负载。此外，阵列之间的本地数据线通过交换机连接。因此，通过关于单元阵列阵列的地址信息来打开/关闭开关，从而防止本地数据线的不必要的线路加载以完全消除不必要的负载。此外，本发明减少了线路负载，从而提高了数据处理速度。

8. 发明授权

US08164195B2 Pad structure of semiconductor integrated circuit apparatus 有权
标题翻译：半导体集成电路设备的焊盘结构
公开(公告)号：US08164195B2
公开(公告)日：2012-04-24
申请号：US12336390
申请日：2008-12-16
申请人： Sung-Soo Chi
发明人： Sung-Soo Chi
IPC分类号： H01L23/488
CPC分类号： H01L24/05 , H01L23/5226 , H01L23/585 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05556 , H01L2224/05599 , H01L2224/451 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： A pad structure of a semiconductor integrated circuit apparatus includes a semiconductor substrate upon which circuit patterns forming a device are disposed, a pad disposed on an uppermost part of the semiconductor substrate, and a plurality of fixing parts, each disposed along opposing edge portions of the pad to fix the pad and the semiconductor substrate to each other.
摘要翻译：半导体集成电路装置的焊盘结构包括半导体基板，其上设置有形成器件的电路图案，设置在半导体基板的最上部的焊盘和多个固定部件，每个固定部件沿着相对的边缘部分衬垫将衬垫和半导体衬底彼此固定。

9. 发明授权

US07706200B2 Internal voltage generator 失效
标题翻译：内部电压发生器
公开(公告)号：US07706200B2
公开(公告)日：2010-04-27
申请号：US12357641
申请日：2009-01-22
申请人： Sung-Soo Chi
发明人： Sung-Soo Chi
IPC分类号： G11C7/00 , G11C7/06 , G11C7/08 , G11C7/12
CPC分类号： G05F1/465 , G11C5/14
摘要： An internal voltage generation device includes a plurality of output nodes; a bit line precharge voltage generation unit for generating a bit line precharge voltage; a first voltage drop unit for transferring the bit line precharge voltage to a first output node after decreasing the bit line precharge voltage by a first voltage drop amount in response to a test mode signal; and a second voltage drop unit for transferring the bit line precharge voltage to a second output node after decreasing the bit line precharge voltage by a second voltage drop amount in response to the test mode signal, wherein the second voltage drop amount is greater than the first voltage drop amount.
摘要翻译：内部电压产生装置包括多个输出节点; 位线预充电电压产生单元，用于产生位线预充电电压; 第一电压降单元，用于响应于测试模式信号，在将位线预充电电压降低第一电压降量之后，将位线预充电电压传送到第一输出节点; 以及第二电压降单元，用于响应于所述测试模式信号而将所述位线预充电电压降低第二电压降量，将所述位线预充电电压传送到第二输出节点，其中所述第二电压降量大于所述第一输出节点电压降量。

10. 发明申请

US20080239838A1 Semiconductor memory device for reducing power consumption 有权
标题翻译：用于降低功耗的半导体存储器件
公开(公告)号：US20080239838A1
公开(公告)日：2008-10-02
申请号：US12003548
申请日：2007-12-28
申请人： Sung-Soo Chi , Jae-Jin Lee
发明人： Sung-Soo Chi , Jae-Jin Lee
IPC分类号： G11C7/22 , G11C5/14
CPC分类号： G11C11/4085 , G11C8/08
摘要： A semiconductor memory device which includes: a voltage supplying unit for outputting a power source voltage as a driving source signal during a predetermined time, and then outputting a high voltage as the driving source signal in response to a driving control signal activated in response to an address signal; and a word line control unit for activating a word line at a voltage level of the driving source signal in response to the driving control signal.
摘要翻译：一种半导体存储器件，包括：电压提供单元，用于在预定时间期间输出作为驱动源信号的电源电压，然后响应于响应于所述驱动源信号而被激活的驱动控制信号输出高电压作为驱动源信号地址信号以及字线控制单元，用于响应于驱动控制信号而在驱动源信号的电压电平下激活字线。

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