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1. 发明授权

US08270671B1 Method and system for generic object detection using block features 失效
标题翻译：使用块特征的通用对象检测的方法和系统
公开(公告)号：US08270671B1
公开(公告)日：2012-09-18
申请号：US12380415
申请日：2009-02-27
申请人： Swarup Medasani , Rahul Shringarpure
发明人： Swarup Medasani , Rahul Shringarpure
IPC分类号： G06K9/00
CPC分类号： G06K9/00986 , G06K9/4642 , G06K9/6202
摘要： Disclosed is a method and system for generic object detection using block-based feature computation and, more specifically, a method and system for massively parallel computation of object features sets according to an optimized clock-cycle matrix. The method uses an array of correlators to calculate block sums for each section of the image to be analyzed. A greedy heuristic scheduling algorithm is executed to produce an optimized clock cycle matrix such that overlapping features which use the same block sum do not attempt to access the block at the same time, thereby avoiding race memory conditions. The processing system can employ any of a variety of hardwired Very Large Scale Integration (VLSI) chips such as Field Programmable Gate Arrays (FPGAs), Digital Signal Processors (DSPs) and Application Specific Integrated Circuits (ASICs).
摘要翻译：公开了一种使用基于块的特征计算的通用对象检测的方法和系统，更具体地，涉及根据优化的时钟周期矩阵对对象特征集进行大规模并行计算的方法和系统。该方法使用相关器阵列来计算待分析图像的每个部分的块和。执行贪婪启发式调度算法以产生优化的时钟周期矩阵，使得使用相同块和的重叠特征不尝试同时访问块，从而避免竞态存储器条件。处理系统可以采用各种硬连线超大规模集成（VLSI）芯片，例如现场可编程门阵列（FPGA），数字信号处理器（DSP）和专用集成电路（ASIC）。

2. 发明授权

US08433098B1 Method and system for generic object detection using block features 失效
标题翻译：使用块特征的通用对象检测的方法和系统
公开(公告)号：US08433098B1
公开(公告)日：2013-04-30
申请号：US13535098
申请日：2012-06-27
申请人： Swarup Medasani , Rahul Shringarpure
发明人： Swarup Medasani , Rahul Shringarpure
IPC分类号： G06K9/00
CPC分类号： G06K9/00986 , G06K9/4642 , G06K9/6202
摘要： Disclosed is a method and system for generic object detection using block-based feature computation and, more specifically, a method and system for massively parallel computation of object features sets according to an optimized clock-cycle matrix. The method uses an array of correlators to calculate block sums for each section of the image to be analyzed. A greedy heuristic scheduling algorithm is executed to produce an optimized clock cycle matrix such that overlapping features which use the same block sum do not attempt to access the block at the same time, thereby avoiding race memory conditions. The processing system can employ any of a variety of hardwired Very Large Scale Integration (VLSI) chips such as Field Programmable Gate Arrays (FPGAs), Digital Signal Processors (DSPs) and Application Specific Integrated Circuits (ASICs).
摘要翻译：公开了一种使用基于块的特征计算的通用对象检测的方法和系统，更具体地，涉及根据优化的时钟周期矩阵对对象特征集进行大规模并行计算的方法和系统。该方法使用相关器阵列来计算待分析图像的每个部分的块和。执行贪婪启发式调度算法以产生优化的时钟周期矩阵，使得使用相同块和的重叠特征不尝试同时访问块，从而避免竞态存储器条件。处理系统可以采用各种硬连线超大规模集成（VLSI）芯片，例如现场可编程门阵列（FPGA），数字信号处理器（DSP）和专用集成电路（ASIC）。

3. 发明授权

US08035435B1 Divided clock synchronization 有权
标题翻译：分时钟同步
公开(公告)号：US08035435B1
公开(公告)日：2011-10-11
申请号：US12567596
申请日：2009-09-25
申请人： Rahul Shringarpure , Cynthia D. Baringer
发明人： Rahul Shringarpure , Cynthia D. Baringer
IPC分类号： H03L7/00
CPC分类号： H04J3/0685 , H03K5/135 , H03K5/15026 , H04J3/047
摘要： Circuits, demultiplexers, and methods are disclosed. A circuit includes a reference clock input to receive clock pulses at a reference clock speed. An internal divided clock input receives a divided clock signal from a clock divider that is driven by the clock pulses. The clock divider generates the divided clock signal at a second clock speed that is a fraction of the reference clock speed. An external divided clock input receives an external divided clock signal. The external divided clock signal is driven by the clock pulses and operates at the second clock speed. A clock transition synchronization circuit suppresses application of one or more of the clock pulses to the clock divider when the divided clock signal transitions between clock states out of synchronization with the external divided clock signal.
摘要翻译：公开了电路，解复用器和方法。电路包括用于以参考时钟速度接收时钟脉冲的参考时钟输入。内部分频时钟输入接收来自由时钟脉冲驱动的时钟分频器的分频时钟信号。时钟分频器以第二个时钟速度产生分频时钟信号，该时钟速度是参考时钟速度的一小部分。外部分频时钟输入接收外部分频时钟信号。外部分频时钟信号由时钟脉冲驱动，并以第二时钟速度工作。当分频时钟信号在与外部分频时钟信号不同步的时钟状态之间转变时，时钟转换同步电路抑制一个或多个时钟脉冲施加到时钟分频器。

4. 发明申请

US20100269022A1 Circuits And Methods For Dual Redundant Register Files With Error Detection And Correction Mechanisms 有权
标题翻译：具有错误检测和校正机制的双冗余寄存器文件的电路和方法
公开(公告)号：US20100269022A1
公开(公告)日：2010-10-21
申请号：US12626488
申请日：2009-11-25
申请人： Lawrence T. Clark , Dan W. Patterson , Xiaoyin Yao , David Pettit , Rahul Shringarpure
发明人： Lawrence T. Clark , Dan W. Patterson , Xiaoyin Yao , David Pettit , Rahul Shringarpure
IPC分类号： H03M13/05 , G06F12/00 , G06F11/10
CPC分类号： G06F11/183 , G06F9/3867 , G06F11/1008 , G06F11/1407 , G06F11/1629 , G06F12/0802 , G06F12/1027
摘要： Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein.
摘要翻译：本文描述了具有错误检测和校正机制的双重冗余寄存器文件的电路和方法的实施例。本文还描述了其它实施例和相关示例。

5. 发明授权

US08397133B2 Circuits and methods for dual redundant register files with error detection and correction mechanisms 有权
标题翻译：具有错误检测和校正机制的双冗余寄存器文件的电路和方法
公开(公告)号：US08397133B2
公开(公告)日：2013-03-12
申请号：US12626488
申请日：2009-11-25
申请人： Lawrence T. Clark , Dan W. Patterson , Xiaoyin Yao , David Pettit , Rahul Shringarpure
发明人： Lawrence T. Clark , Dan W. Patterson , Xiaoyin Yao , David Pettit , Rahul Shringarpure
IPC分类号： G06F11/00
CPC分类号： G06F11/183 , G06F9/3867 , G06F11/1008 , G06F11/1407 , G06F11/1629 , G06F12/0802 , G06F12/1027
摘要： Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein.
摘要翻译：本文描述了具有错误检测和校正机制的双重冗余寄存器文件的电路和方法的实施例。本文还描述了其它实施例和相关示例。

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