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1. 发明授权

US09547740B2 Methods for fabricating high-density integrated circuit devices 有权
标题翻译：制造高密度集成电路器件的方法
公开(公告)号：US09547740B2
公开(公告)日：2017-01-17
申请号：US14584786
申请日：2014-12-29
申请人： SYNOPSYS, INC.
发明人： Victor Moroz , Xi-Wei Lin
IPC分类号： G06F17/50 , H01L21/308
CPC分类号： G06F17/5068 , H01L21/3086
摘要： An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process.
摘要翻译：描述了具有多条线的集成电路器件，其中线的宽度和相邻线之间的间距在小范围内变化，该范围独立于由于光刻工艺或其它图案化工艺引起的变化，涉及制造设备。描述了用于形成用于线路的蚀刻掩模的顺序侧壁间隔物形成工艺，其导致以交替方式布置的第一组和第二组侧壁间隔件。作为这种顺序侧壁间隔工艺的结果，跨越多条线的线的宽度的变化以及相邻线之间的间隔取决于侧壁间隔件的尺寸的变化。这些变化与由图案化工艺引起的中间掩模元件的尺寸变化相比，分布远远小于分布，并且可以被控制。

2. 发明授权

US09379018B2 Increasing Ion/Ioff ratio in FinFETs and nano-wires 有权
标题翻译：增加FinFET和纳米线中的离子/离子比率
公开(公告)号：US09379018B2
公开(公告)日：2016-06-28
申请号：US14491908
申请日：2014-09-19
申请人： SYNOPSYS, INC.
发明人： Munkang Choi , Victor Moroz , Xi-Wei Lin
IPC分类号： H01L21/8234 , H01L29/66 , H01L29/78 , H01L27/088 , B82Y10/00 , H01L29/423 , H01L29/775 , H01L29/06 , H01L29/40
CPC分类号： H01L21/823431 , B82Y10/00 , H01L27/0886 , H01L29/0673 , H01L29/105 , H01L29/1054 , H01L29/402 , H01L29/42376 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/7853
摘要： Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain volumes with a channel between, a gate stack disposed outside the body and facing at least one of the surfaces of the body along the channel. The body contains an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced longitudinally from both the source/drain volumes. The adjustment volume comprises an adjustment volume material having, at each longitudinal position, an electrical conductivity which differs from that of the adjacent body material at the same longitudinal position, at least while the transistor is in an off-state. In one embodiment the adjustment volume material is a dielectric. In another embodiment the adjustment volume material is an electrical conductor.
摘要翻译：粗略地描述，集成电路晶体管结构具有半导体材料体，该主体具有两个纵向间隔开的掺杂源极/漏极体积，其间具有通道，位于主体外部并面向主体的至少一个表面的栅极堆叠这个频道。主体在通道容积内纵向地包含调节体积，并且在第一表面之后隔开第一距离并且与源/排出体积纵向隔开。调节体积包括至少在晶体管处于截止状态时在每个纵向位置处具有不同于相同主体材料在同一纵向位置的电导率的调节体积材料。在一个实施例中，调节体积材料是电介质。在另一个实施例中，调节体积材料是电导体。

3. 发明授权

US09147027B2 Chip cross-section identification and rendering during failure analysis 有权
标题翻译：故障分析期间的芯片截面识别和渲染
公开(公告)号：US09147027B2
公开(公告)日：2015-09-29
申请号：US14318552
申请日：2014-06-27
申请人： Synopsys, Inc.
发明人： Xi-Wei Lin , Ankush Oberai
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068
摘要： A defective integrated circuit (IC) is analyzed to identify a portion of the integrated circuit possibly containing an electrical defect. A computer is used to process the design information of the integrated circuit and to navigate to the physical portion of the integrated circuit where potential electrical defect might be found. The design information includes information on the layout and the technology used to fabricate the integrated circuit. A three-dimensional view of the portion of the design of integrated circuit where the electrical defect might be found is rendered, based on the design information for the integrated circuit.
摘要翻译：分析有缺陷的集成电路（IC）以识别可能包含电缺陷的集成电路的一部分。计算机用于处理集成电路的设计信息，并导航到可能发现潜在电气缺陷的集成电路的物理部分。设计信息包括用于制造集成电路的布局和技术信息。基于集成电路的设计信息，呈现出可能发现电气缺陷的集成电路设计部分的三维视图。

4. 发明申请

US20130332893A1 FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM 有权
公开(公告)号：US20130332893A1
公开(公告)日：2013-12-12
申请号：US13936572
申请日：2013-07-08
申请人： Synopsys, Inc.
发明人： Xi-Wei Lin , Jyh-Chwen Frank Lee , Dipankar Pramanik
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5068 , H01L27/0207
摘要： A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.

5. 发明授权

US10482212B2 Automated resistance and capacitance extraction and netlist generation of logic cells 有权
公开(公告)号：US10482212B2
公开(公告)日：2019-11-19
申请号：US15901749
申请日：2018-02-21
申请人： Synopsys, Inc.
发明人： Zudian Qin , Karim El Sayed , Victor Moroz , Xi-Wei Lin
IPC分类号： G06F17/50 , H01L27/02
摘要： Disclosed is technology for evaluating the performance, power, area, and cost of a new or significantly modified IC fabrication process. A layout of a circuit design is provided, the circuit design including pins, transistors, and interconnects. The interconnects have at least two endpoints, each of the endpoints being either a terminal of a transistor or a pin in the circuit design. The locations for a plurality of transistor and interconnect endpoints in the layout are identified. A three-dimensional circuit representation is fabricated in accordance with the layout and the fabrication process. Parasitic resistance and capacitance values are estimated for pairs of interconnect endpoints which share an interconnect in the three-dimensional circuit representation. An annotated netlist is developed for the plurality of the transistors interconnects endpoints identified from the layout, and which further indicates the parasitic resistance values and parasitic capacitance values estimated from the three-dimensional circuit representation.

6. 发明授权

US10311200B2 Pre-silicon design rule evaluation 有权
公开(公告)号：US10311200B2
公开(公告)日：2019-06-04
申请号：US15227863
申请日：2016-08-03
申请人： Synopsys, Inc.
发明人： Victor Moroz , Karim El Sayed , Terry Sylvan Kam-Chiu Ma , Xi-Wei Lin , Qiang Lu
IPC分类号： G06F17/50
摘要： Roughly described, a method for developing a set of design rules for a fabrication process in development includes, for each of several candidate DRUTs for the fabrication process, laying our a logic cell based on the DRUT, the logic cell having at least one transistor and at least one interconnect, simulating fabrication of the logic cell according to the fabrication process and the layout, simulating behavior of the logic cell structure, including characterizing the combined behavior of both the first transistor and the first interconnect, evaluating performance of the logic cell structure in dependence upon the behavior as characterized, and recording in a database, in association with an indication of the DRUT, values indicating performance of the logic cell. The database can be used to select the best DRUT for the fabrication process.

7. 发明申请

US20170039308A1 Pre-Silicon Design Rule Evaluation 审中-公开
标题翻译：硅片前设计规则评估
公开(公告)号：US20170039308A1
公开(公告)日：2017-02-09
申请号：US15227863
申请日：2016-08-03
申请人： Synopsys, Inc.
发明人： Victor Moroz , Karim El Sayed , Terry Sylvan Kam-Chiu Ma , Xi-Wei Lin , Qiang Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036
摘要： Roughly described, a method for developing a set of design rules for a fabrication process in development includes, for each of several candidate DRUTs for the fabrication process, laying our a logic cell based on the DRUT, the logic cell having at least one transistor and at least one interconnect, simulating fabrication of the logic cell according to the fabrication process and the layout, simulating behavior of the logic cell structure, including characterizing the combined behavior of both the first transistor and the first interconnect, evaluating performance of the logic cell structure in dependence upon the behavior as characterized, and recording in a database, in association with an indication of the DRUT, values indicating performance of the logic cell. The database can be used to select the best DRUT for the fabrication process.
摘要翻译：粗略地描述，用于开发用于开发中的制造工艺的一组设计规则的方法包括针对制造工艺的几个候选DRUT中的每一个，基于DRUT铺设我们的逻辑单元，所述逻辑单元具有至少一个晶体管和至少一个互连，根据制造过程和布局模拟逻辑单元的制造，模拟逻辑单元结构的行为，包括表征第一晶体管和第一互连两者的组合行为，评估逻辑单元结构的性能根据表征的行为，并且与数据库中的DRUT的指示相关联地记录指示逻辑单元的性能的值。数据库可用于为制造过程选择最佳DRUT。

8. 发明申请

US20160019331A1 CHIP CROSS-SECTION IDENTIFICATION AND RENDERING ANALYSIS 有权
标题翻译：芯片交叉部分识别和渲染分析
公开(公告)号：US20160019331A1
公开(公告)日：2016-01-21
申请号：US14867822
申请日：2015-09-28
申请人： Synopsys, Inc.
发明人： Xi-Wei Lin , Ankush Oberai
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068
摘要： A defective integrated circuit (IC) is analyzed to identify a portion of the integrated circuit possibly containing an electrical defect. A computer is used to process the design information of the integrated circuit and to navigate to the physical portion of the integrated circuit where the potential electrical defect might be found. The design information includes information on the layout and the technology used to fabricate the integrated circuit. A three-dimensional view of the portion of the design of the integrated circuit where the electrical defect might be found is rendered, based on the design information for the integrated circuit.
摘要翻译：分析有缺陷的集成电路（IC）以识别可能包含电缺陷的集成电路的一部分。计算机用于处理集成电路的设计信息，并导航到可能发现潜在电气缺陷的集成电路的物理部分。设计信息包括用于制造集成电路的布局和技术信息。基于集成电路的设计信息，可以获得可能发现电气缺陷的集成电路的设计部分的三维视图。

9. 发明申请

US20230023073A1 INPUT/OUTPUT DEVICES THAT ARE COMPATIBLE WITH GATE-ALL-AROUND TECHNOLOGY 有权
公开(公告)号：US20230023073A1
公开(公告)日：2023-01-26
申请号：US17870662
申请日：2022-07-21
申请人： Synopsys, Inc.
发明人： Victor Moroz , Robert B. Lefferts , Xi-Wei Lin , Munkang Choi
IPC分类号： H01L29/423 , H01L27/088 , H01L29/786 , H01L29/66
摘要： An integrated circuit (IC) chip may include a first gate-all-around (GAA) device and a second GAA device. The first GAA device may include a first set of silicon dioxide structures around a first set of silicon channels, a first set of hafnium dioxide structures around the first set of silicon dioxide structures, and a first metal structure around the first set of hafnium dioxide structures. The second GAA device may include a second set of silicon dioxide structures around a second set of silicon channels, and a second metal structure around the second set of silicon dioxide structures. Each silicon dioxide structure in the first set of silicon dioxide structures may have a first thickness. Each silicon dioxide structure in the second set of silicon dioxide structures may have a second thickness, which is greater than the first thickness.

10. 发明申请

US20220172953A1 FIN PATTERNING TO REDUCE FIN COLLAPSE AND TRANSISTOR LEAKAGE 有权
公开(公告)号：US20220172953A1
公开(公告)日：2022-06-02
申请号：US17109504
申请日：2020-12-02
申请人： Synopsys, Inc.
发明人： Victor Moroz , Xi-Wei Lin
IPC分类号： H01L21/3065 , H01L21/308 , H01L29/66 , G06F30/392 , G06F30/398
摘要： At least one fin structure may be created on a silicon substrate. Next, a width of the at least one fin structure may be decreased by applying one or more iterations of a self-limiting fin etch process.

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