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1. 发明授权

US10510566B2 Cluster tool techniques with improved efficiency 有权
公开(公告)号：US10510566B2
公开(公告)日：2019-12-17
申请号：US14798938
申请日：2015-07-14
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Su-Horng Lin , Tsung-Hsun Yu , Victor Y. Lu
IPC分类号： H01L21/67 , C30B25/02
摘要： Some embodiments relate to a cluster tool for semiconductor manufacturing. The cluster tool comprises a first transfer chamber having a first transfer robot. The cluster tool further comprises a designated storage chamber and a transfer load lock attached to the first transfer chamber. The cluster tool further comprises a second transfer chamber connected to the first transfer chamber through a pair of via connector chambers, the second transfer chamber having a second transfer robot. The cluster tool further comprises at least three epitaxial deposition chamber attached to the second transfer chamber. The cluster tool further comprises a control unit configured to control the second transfer robot to transfer wafers between the designated storage chamber and the transfer load lock.

2. 发明授权

US10460999B2 Metrology device and metrology method thereof 有权
公开(公告)号：US10460999B2
公开(公告)日：2019-10-29
申请号：US14092256
申请日：2013-11-27
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Su-Horng Lin , Chi-Ming Yang
IPC分类号： G01N23/00 , H01L21/66
摘要： A metrology device includes a light source and an image sensor. The light source is configured for providing an X-ray illuminating a wafer. The image sensor is configured for detecting a spatial domain pattern produced when the X-ray illuminating the wafer.

3. 发明授权

US09543141B2 Method for curing flowable layer 有权
标题翻译：固化流动层的方法
公开(公告)号：US09543141B2
公开(公告)日：2017-01-10
申请号：US14564304
申请日：2014-12-09
申请人： Taiwan Semiconductor Manufacturing Co., Ltd
发明人： Chi-Ming Liao , Ker-Hsun Liao , Chun-Ou Liu , Su-Horng Lin
IPC分类号： H01L21/02 , H01L21/3105
CPC分类号： H01L21/02318 , H01L21/02126 , H01L21/02164 , H01L21/02205 , H01L21/02271 , H01L21/02282 , H01L21/02326 , H01L21/3105 , H01L29/66545
摘要： Methods for forming a semiconductor structure are provided. The method for forming a semiconductor structure includes forming a flowable layer over a substrate and heating the flowable layer to form a cured layer in a curing process. In addition, the curing process is performed under a pressure of over 2 atmospheres, and the flowable layer reacts with precursors in the flowable layer during the curing process.
摘要翻译：提供了形成半导体结构的方法。形成半导体结构的方法包括在基板上形成可流动层，并在固化过程中加热可流动层以形成固化层。此外，固化过程在超过2个大气压的压力下进行，并且可流动层在固化过程中与可流动层中的前体反应。

4. 发明申请

US20160013043A1 BOTTOM-UP PEALD PROCESS 审中-公开
标题翻译：底层PEALD工艺
公开(公告)号：US20160013043A1
公开(公告)日：2016-01-14
申请号：US14861441
申请日：2015-09-22
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Lin-Jung Wu , Su-Horng Lin , Chi-Ming Yang
IPC分类号： H01L21/02 , H01L21/687 , H01L21/285
CPC分类号： H01L21/0228 , C23C16/045 , C23C16/45542 , H01J37/321 , H01J37/3211 , H01J37/32357 , H01J37/32706 , H01J37/32926 , H01L21/02274 , H01L21/28556 , H01L21/687
摘要： The present disclosure relates to a method and apparatus for performing a plasma enhanced ALD (PEALD) process that provides for improved step coverage. The process introduces a precursor gas into a processing chamber comprising a semiconductor workpiece. The first gas is ionized to from a plurality of ionized precursor molecules. A bias voltage is subsequently applied to the workpiece. The bias voltage attracts the ionized precursor molecules to the workpiece, so as to provide anisotropic coverage of the workpiece with the precursor gas. A reactant gas is introduced into the processing chamber. A plasma is subsequently ignited from the reactant gas, causing the reactant gas to react with the ionized precursor molecules that have been deposited onto the substrate to form a deposited layer on the workpiece.
摘要翻译：本公开涉及一种用于执行等离子体增强ALD（PEALD）过程的方法和装置，其提供改进的步骤覆盖。该方法将前体气体引入到包括半导体工件的处理室中。将第一气体从多个离子化的前体分子离子化。随后将偏置电压施加到工件。偏置电压将离子化的前体分子吸引到工件，以便为前体气体提供工件的各向异性覆盖。将反应气体引入处理室。等离子体随后从反应气体中点燃，使反应气体与沉积在基底上的离子化前体分子反应，在工件上形成沉积层。

5. 发明授权

US11414759B2 Mechanisms for supplying process gas into wafer process apparatus 有权
公开(公告)号：US11414759B2
公开(公告)日：2022-08-16
申请号：US14093084
申请日：2013-11-29
申请人： Taiwan Semiconductor Manufacturing Co., Ltd
发明人： Su-Horng Lin
IPC分类号： C23C16/458 , C23C16/455 , C23C16/44 , C30B25/14 , C30B25/02 , C30B25/16 , H01J37/32 , H01L21/205
摘要： Embodiments of mechanisms for processing a semiconductor wafer are provided. A method for processing a wafer includes providing a wafer process apparatus. The wafer process apparatus includes a chamber and a stage positioned in the chamber for supporting the semiconductor wafer. The method also includes supplying a process gas to the semiconductor wafer via a discharging assembly that is adjacent to the stage. The discharging assembly includes a discharging passage configured without a vertical flow path section.

6. 发明授权

US10755953B2 Cluster tool techniques with improved efficiency 有权
公开(公告)号：US10755953B2
公开(公告)日：2020-08-25
申请号：US16656804
申请日：2019-10-18
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Su-Horng Lin , Tsung-Hsun Yu , Victor Y. Lu
IPC分类号： H01L21/67 , H01L21/677 , C30B25/02
摘要： The present disclosure relates to some embodiments of a method for improving processing efficiency of a cluster tool. The method comprises transferring a first lot of wafers from a transfer load lock to a designated storage load lock and transferring a second lot of wafers from the transfer load lock to the designated storage load lock while the first lot of wafers is in the transfer load lock or the designated storage load lock. The designated storage load lock has the same structure as the transfer load lock and respectively has an inner load lock portal at an interface with the first transfer chamber and an outer load lock portal on a sidewall of a front end interface. The inner load lock portal of the designated storage load lock is retained opened during processing. The outer load lock portal of the designated storage load lock is retained closed during processing.

7. 发明申请

US20200051837A1 CLUSTER TOOL TECHNIQUES WITH IMPROVED EFFICIENCY 审中-公开
公开(公告)号：US20200051837A1
公开(公告)日：2020-02-13
申请号：US16656804
申请日：2019-10-18
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Su-Horng Lin , Tsung-Hsun Yu , Victor Y. Lu
IPC分类号： H01L21/67 , H01L21/677
摘要： The present disclosure relates to some embodiments of a method for improving processing efficiency of a cluster tool. The method comprises transferring a first lot of wafers from a transfer load lock to a designated storage load lock and transferring a second lot of wafers from the transfer load lock to the designated storage load lock while the first lot of wafers is in the transfer load lock or the designated storage load lock. The designated storage load lock has the same structure as the transfer load lock and respectively has an inner load lock portal at an interface with the first transfer chamber and an outer load lock portal on a sidewall of a front end interface. The inner load lock portal of the designated storage load lock is retained opened during processing. The outer load lock portal of the designated storage load lock is retained closed during processing.

8. 发明申请

US20170025291A1 MULTI-CHAMBER FURNACE FOR BATCH PROCESSING 审中-公开
标题翻译：用于批量加工的多功能炉
公开(公告)号：US20170025291A1
公开(公告)日：2017-01-26
申请号：US14805584
申请日：2015-07-22
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Su-Horng Lin
IPC分类号： H01L21/67 , C23C16/458 , F27B5/02 , H01L21/66 , H01L21/687 , H01L21/677 , H01L21/02 , H01L21/324 , C23C16/455 , F27B5/12
CPC分类号： H01L22/20 , F27B5/02 , F27B5/12 , H01L21/0223 , H01L21/02255 , H01L21/324 , H01L21/67109 , H01L21/67167
摘要： A multi-chamber furnace for processing at least 100 substrates is provided. Reactor housings define a plurality of laterally spaced reactor chambers that are individually configured to accommodate up to about 50 substrates. Substrate holders correspond to the reactor chambers, and are configured to support and vertically stack substrates arranged in the corresponding reactor chambers. Heaters correspond to the reactor chambers and are configured to heat the corresponding reactor chambers. A method for batch processing substrates using the multi-chamber furnace is also provided.
摘要翻译：提供了一种用于处理至少100个基板的多室炉。反应器壳体限定多个横向间隔开的反应室，其被单独构造成容纳多达约50个基板。基板保持件对应于反应室，并且构造成支撑并垂直堆叠布置在相应的反应器室中的基板。加热器对应于反应室，并且构造成加热相应的反应室。还提供了使用多室炉的批处理衬底的方法。

9. 发明授权

US09435048B2 Layer by layer electro chemical plating (ECP) process 有权
标题翻译：逐层电化学镀（ECP）工艺
公开(公告)号：US09435048B2
公开(公告)日：2016-09-06
申请号：US13778412
申请日：2013-02-27
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Su-Horng Lin , Chi-Ming Yang
IPC分类号： C25D5/18 , C25D7/12 , C25D21/12 , C25D17/00
CPC分类号： C25D5/18 , C25D7/12 , C25D17/001 , C25D21/12
摘要： The present disclosure relates to an electro-chemical plating (ECP) process that provides for an isotropic deposition, and a related apparatus. In some embodiments, the disclosed ECP process is performed by providing a substrate into an electroplating solution comprising a plurality of ions of a material to be deposited. A periodic patterned signal, which alternates between a first value and a different second value, is applied to the substrate. When the periodic patterned signal is at the first value, ions from the electroplating solution affix to the substrate. When the periodic patterned signal is at the second value, ions from the electroplating solution do not affix to the substrate. By using the periodic patterned signal to perform electro-chemical plating, the deposition rate of the plating process is reduced, resulting in an isotropic deposition over the substrate that mitigates gap fill problems (e.g., void formation).
摘要翻译：本公开涉及提供各向同性沉积的电化学电镀（ECP）工艺，以及相关设备。在一些实施方案中，所公开的ECP方法是通过将衬底提供到包括待沉积材料的多个离子的电镀溶液中来进行的。在第一值和不同的第二值之间交替的周期性图案化信号被施加到衬底。当周期性图案化信号处于第一值时，来自电镀溶液的离子粘附到基底上。当周期性图案化信号处于第二值时，来自电镀溶液的离子不贴附到衬底上。通过使用周期性图案化信号进行电化学电镀，电镀工艺的沉积速率降低，导致衬底上的各向同性沉积，以减轻间隙填充问题（例如，空隙形成）。

10. 发明申请

US20140238864A1 Layer by Layer Electro Chemical Plating (ECP) Process 有权
标题翻译：逐层电化学镀（ECP）工艺
公开(公告)号：US20140238864A1
公开(公告)日：2014-08-28
申请号：US13778412
申请日：2013-02-27
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
发明人： Su-Horng Lin , Chi-Ming Yang
IPC分类号： C25D5/18 , C25D17/00 , C25D21/12 , C25D7/12
CPC分类号： C25D5/18 , C25D7/12 , C25D17/001 , C25D21/12
摘要： The present disclosure relates to an electro-chemical plating (ECP) process that provides for an isotropic deposition, and a related apparatus. In some embodiments, the disclosed ECP process is performed by providing a substrate into an electroplating solution comprising a plurality of ions of a material to be deposited. A periodic patterned signal, which alternates between a first value and a different second value, is applied to the substrate. When the periodic patterned signal is at the first value, ions from the electroplating solution affix to the substrate. When the periodic patterned signal is at the second value, ions from the electroplating solution do not affix to the substrate. By using the periodic patterned signal to perform electro-chemical plating, the deposition rate of the plating process is reduced, resulting in an isotropic deposition over the substrate that mitigates gap fill problems (e.g., void formation).
摘要翻译：本公开涉及提供各向同性沉积的电化学电镀（ECP）工艺，以及相关设备。在一些实施方案中，所公开的ECP方法是通过将衬底提供到包括待沉积材料的多个离子的电镀溶液中来进行的。在第一值和不同的第二值之间交替的周期性图案化信号被施加到衬底。当周期性图案化信号处于第一值时，来自电镀溶液的离子粘附到基底上。当周期性图案化信号处于第二值时，来自电镀溶液的离子不贴附到衬底上。通过使用周期性图案化信号进行电化学电镀，电镀工艺的沉积速率降低，导致衬底上的各向同性沉积，从而缓解间隙填充问题（例如，空隙形成）。

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