专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US11101359B2 Gate-all-around (GAA) method and devices 有权
公开(公告)号：US11101359B2
公开(公告)日：2021-08-24
申请号：US16409386
申请日：2019-05-10
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shien-Yang Wu , Ta-Chun Lin , Kuo-Hua Pan
IPC分类号： H01L29/423 , H01L29/06 , H01L21/8234 , H01L21/3065 , H01L29/66 , H01L27/088 , H01L21/02 , H01L21/762 , H01L21/306 , H01L29/40 , H01L29/165 , H01L21/027
摘要： A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

2. 发明申请

US20200098687A1 Electrical Fuse Structure and Method of Formation 审中-公开
公开(公告)号：US20200098687A1
公开(公告)日：2020-03-26
申请号：US16696929
申请日：2019-11-26
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shien-Yang Wu , Wei-Chang Kung
IPC分类号： H01L23/525
摘要： Various fuse structures are disclosed herein that exhibit improved performance, such as reduced electro-migration. An exemplary fuse structure includes an anode, a cathode, and a fuse link extending between the anode and the cathode. A plurality of anode contacts are coupled to the anode, and a plurality of cathode contacts are coupled to the cathode. The plurality of cathode contacts are arranged symmetrically with respect to a centerline of the fuse link.

3. 发明授权

US10014066B2 Anti-fuse cell structure including reading and programming devices with different gate dielectric thickness 有权
公开(公告)号：US10014066B2
公开(公告)日：2018-07-03
申请号：US15004329
申请日：2016-01-22
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jhon Jhy Liaw , Shien-Yang Wu
IPC分类号： G11C17/00 , G11C17/18 , H01L23/525 , H01L23/528 , H01L29/78 , H01L29/94 , G11C17/16 , H01L27/112
CPC分类号： H01L27/112 , G11C17/16 , G11C17/18 , H01L23/5252 , H01L23/528 , H01L27/0886 , H01L27/11206 , H01L29/7851 , H01L29/94
摘要： A structure includes a word-line, a bit-line, and an anti-fuse cell. The anti-fuse cell includes a reading device, which includes a first gate electrode connected to the word-line, a first gate dielectric underlying the first gate electrode, a drain region connected to the bit-line, and a source region. The first gate dielectric has a first thickness. The drain region and the source region are on opposite sides of the first gate electrode. The anti-fuse cell further includes a programming device including a second gate electrode connected to the word-line, and a second gate dielectric underlying the second gate electrode. The second gate dielectric has a second thickness smaller than the first thickness. The programming device further includes a source/drain region connected to the source region of the reading device.

4. 发明申请

US20170345758A1 Electrical Fuse Structure and Method of Formation 审中-公开
公开(公告)号：US20170345758A1
公开(公告)日：2017-11-30
申请号：US15677881
申请日：2017-08-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shien-Yang Wu , Wei-Chang Kung
IPC分类号： H01L23/525 , H01L23/522
CPC分类号： H01L23/5256 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Various fuse structures are disclosed herein that exhibit improved performance, such as reduced electro-migration. An exemplary fuse structure includes an anode, a cathode, and a fuse link extending between the anode and the cathode. A plurality of anode contacts are coupled to the anode, and a plurality of cathode contacts are coupled to the cathode. The plurality of cathode contacts are arranged symmetrically with respect to a centerline of the fuse link.

5. 发明申请

US20160358822A1 Bipolar Junction Transistor Formed on Fin Structures 有权
标题翻译：双极结晶体管形成在鳍结构上
公开(公告)号：US20160358822A1
公开(公告)日：2016-12-08
申请号：US15237226
申请日：2016-08-15
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chia-Hsin Hu , Min-chang Liang , Sun-Jay Chang , Shien-Yang Wu
IPC分类号： H01L21/8249 , H01L29/417 , H01L29/10 , H01L29/735 , H01L29/06 , H01L27/06 , H01L29/66
CPC分类号： H01L21/8249 , H01L27/0623 , H01L29/0692 , H01L29/1008 , H01L29/41708 , H01L29/42304 , H01L29/6625 , H01L29/66272 , H01L29/66795 , H01L29/732 , H01L29/735
摘要： A method of forming a Bipolar Junction Transistor (BJT) includes forming an elongated collector line, forming an elongated emitter line parallel to the collector line, and forming an elongated base line parallel to the collector line and positioned between the collector line and the base line. The emitter line, the base line, and the collector line are formed over fin structures.
摘要翻译：形成双极结晶体管（BJT）的方法包括形成细长的收集线，形成平行于集电线的细长发射极线，并且形成平行于集电极线并且位于集电极线和基线之间的细长基线。发射极线，基极线和集电极线形成在鳍结构之上。

6. 发明授权

US09093566B2 High efficiency FinFET diode 有权
标题翻译：高效率FinFET二极管
公开(公告)号：US09093566B2
公开(公告)日：2015-07-28
申请号：US13951202
申请日：2013-07-25
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hsueh-Shih Fan , Sun-Jay Chang , Chia-Hsin Hu , Min-Chang Liang , Shien-Yang Wu , Wen-Hsing Hsieh , Ching-Fang Huang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/861 , H01L29/66 , H01L29/16 , H01L29/161 , H01L29/201 , H01L27/092
CPC分类号： H01L29/7848 , H01L21/0257 , H01L21/26513 , H01L21/823814 , H01L21/823821 , H01L21/823871 , H01L21/823878 , H01L27/0924 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/201 , H01L29/66136 , H01L29/861
摘要： Disclosed are a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.
摘要翻译：公开了一种高效率的FinFET二极管，其设计用于解决由于减小的有效面积而导致的传统FinFET二极管的劣化问题以及制造方法。 FinFET二极管具有掺杂衬底，两个基本上平行的，等间隔的细长半导体鳍结构的两个间隔开的组，在两组之间和用于绝缘的鳍结构之间形成的介电层，多个基本相等间隔并平行垂直于翅片结构的两组横向延伸的细长门结构，以及分别在两组翅片结构上纵向形成的两组半导体条。两组半导体条被掺杂以具有相反的导电类型，p型和n型。 FinFET二极管还具有形成在半导体条上的金属触点。在一个实施例中，半导体条可以通过外延生长和原位掺杂与翅片结构整体形成。

7. 发明申请

US20140319651A1 Electrical Fuse Structure and Method of Formation 有权
标题翻译：电气保险丝结构和形成方法
公开(公告)号：US20140319651A1
公开(公告)日：2014-10-30
申请号：US14333333
申请日：2014-07-16
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shien-Yang Wu , Wei-Chang Kung
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A fuse device having contacts configured to reduce electro-migration is disclosed. In some exemplary embodiments, the fuse structure includes an anode disposed at a first end and a cathode disposed at a second end. A fuse link extends between and contacts the anode and the cathode. A boundary between the fuse link and the cathode has a center point, and each connector of a plurality of cathode connectors has a center point that is an equal distance from the center point of the boundary between the fuse link and the cathode. In some such embodiments, each connector of the plurality of cathode connectors is a different size than an anode connector, whereas in some such embodiments, each connector of the plurality of cathode connectors is substantially a same size as the anode connector along at least one axis.
摘要翻译：公开了具有被配置为减少电迁移的触点的熔断器件。在一些示例性实施例中，熔丝结构包括设置在第一端的阳极和设置在第二端的阴极。熔丝连接件在阳极和阴极之间延伸并与之接触。熔断体和阴极之间的边界具有中心点，并且多个阴极连接器的每个连接器具有与熔断体和阴极之间的边界的中心点相等的中心点。在一些这样的实施例中，多个阴极连接器的每个连接器的尺寸与阳极连接器的尺寸不同，而在一些这样的实施例中，多个阴极连接器的每个连接器与至少一个轴线。

8. 发明授权

US11309244B2 Electrical fuse structure and method of formation 有权
公开(公告)号：US11309244B2
公开(公告)日：2022-04-19
申请号：US15863169
申请日：2018-01-05
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shien-Yang Wu , Wei-Chang Kung
IPC分类号： H01L21/20 , H01L23/525
摘要： An exemplary method includes forming a fuse structure and forming a first cathode connector and a second cathode connector over the fuse structure. The fuse structure includes an anode, a cathode, and a fuse link extending between and connecting the anode and the cathode. The fuse link has a width defined between a first edge and a second edge, which extend a length of the fuse link. The cathode includes a central region defined by a first longitudinal axis and a second longitudinal axis extending respectively from the first edge and the second edge. The first cathode connector and the second cathode connector are equidistant respectively to the fuse link, the first cathode connector does not intersect the first longitudinal axis, and the second cathode connector does not intersect the second longitudinal axis, such that the central region is free of the first cathode connector and the second cathode connector.

9. 发明申请

US20200168715A1 Gate-All-Around (GAA) Method and Devices 审中-公开
公开(公告)号：US20200168715A1
公开(公告)日：2020-05-28
申请号：US16409386
申请日：2019-05-10
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shien-Yang Wu , Ta-Chun Lin , Kuo-Hua Pan
IPC分类号： H01L29/423 , H01L21/02 , H01L29/06 , H01L21/8234 , H01L21/3065 , H01L29/66 , H01L27/088 , H01L21/762 , H01L21/306 , H01L29/40 , H01L29/165
摘要： A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

10. 发明授权

US10521537B2 Method and system of generating layout 有权
公开(公告)号：US10521537B2
公开(公告)日：2019-12-31
申请号：US15881383
申请日：2018-01-26
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shien-Yang Wu , Jye-Yen Cheng , Wei-Chang Kung
IPC分类号： G06F17/50 , H01L23/525
摘要： A method of generating a layout usable for fabricating an integrated circuit is disclosed. The method includes generating a block layout layer usable in conjunction with a first conductive layout layer. The first conductive layout layer includes a fuse layout pattern, and the block layout layer includes a block layout pattern overlapping a portion of a fuse line portion of the fuse layout pattern. A second conductive layout layer is generated to replace the first conductive layout layer. The generating the second conductive layout layer includes performing an optical proximity correction (OPC) process on the first conductive layout layer except the portion of the fuse line portion of the fuse layout pattern corresponding to the block layout pattern.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式