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1. 发明授权

US10957777B2 Semiconductor structure and manufacturing method thereof 有权
公开(公告)号：US10957777B2
公开(公告)日：2021-03-23
申请号：US16663697
申请日：2019-10-25
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
发明人： Che-Cheng Chang , Chih-Han Lin , Horng-Huei Tseng
IPC分类号： H01L29/49 , H01L29/417 , H01L29/40 , H01L21/311 , H01L29/51 , H01L29/06 , H01L21/768
摘要： A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess.

2. 发明授权

US10043887B2 Methods for forming a semiconductor device with a gate stack having angled sidewalls 有权
公开(公告)号：US10043887B2
公开(公告)日：2018-08-07
申请号：US15376610
申请日：2016-12-12
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Che-Cheng Chang , Yi-Jen Chen , Chang-Yin Chen , Yung Jung Chang
IPC分类号： H01L29/66 , H01L29/423 , H01L21/3213 , H01L29/51 , H01L21/3205
摘要： A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided.

3. 发明申请

US20150069535A1 SEMICONDUCTOR DEVICE WITH AN ANGLED SIDEWALL GATE STACK 有权
标题翻译：半导体器件与ANGLED门式门盖
公开(公告)号：US20150069535A1
公开(公告)日：2015-03-12
申请号：US14024848
申请日：2013-09-12
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Che-Cheng Chang , Chang-Yin Chen , Yi - Jen Chen , Yung Jung Chang
IPC分类号： H01L29/423 , H01L29/78 , H01L29/66 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/28114 , H01L21/31116 , H01L21/31138 , H01L21/32055 , H01L21/32135 , H01L21/32137 , H01L29/42376 , H01L29/511 , H01L29/517 , H01L29/6656 , H01L29/78
摘要： A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided.
摘要翻译：半导体器件包括金属栅极叠层。金属栅极堆叠包括高k栅极电介质和位于高k栅极电介质上的金属栅电极。金属栅电极包括与第一顶表面基本上直径相对的第一顶表面和第二底表面。第一顶表面包括第一表面长度，第二底表面包括第二表面长度。第一表面长度大于第二表面长度。提供一种形成半导体器件的方法。

4. 发明申请

US20200058755A1 Semiconductor Structure and Manufacturing Method Thereof 审中-公开
公开(公告)号：US20200058755A1
公开(公告)日：2020-02-20
申请号：US16663697
申请日：2019-10-25
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
发明人： Che-Cheng Chang , Chih-Han Lin , Horng-Huei Tseng
IPC分类号： H01L29/49 , H01L21/768 , H01L29/06 , H01L29/51 , H01L29/417 , H01L21/311 , H01L29/40
摘要： A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess.

5. 发明申请

US20180342600A1 SEMICONDUCTOR DEVICE WITH AN ANGLED SIDEWALL GATE STACK 审中-公开
公开(公告)号：US20180342600A1
公开(公告)日：2018-11-29
申请号：US16055401
申请日：2018-08-06
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
发明人： Che-Cheng Chang , Yi-Jen Chen , Chang-Yin Chen , Yung Jung Chang
IPC分类号： H01L29/66 , H01L21/3213 , H01L29/51 , H01L29/423 , H01L21/28 , H01L21/3205 , H01L21/311 , H01L29/78
摘要： A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided.

6. 发明授权

US10079205B2 Interconnection structure and method of forming the same 有权
公开(公告)号：US10079205B2
公开(公告)日：2018-09-18
申请号：US15722213
申请日：2017-10-02
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
发明人： Che-Cheng Chang , Chih-Han Lin , Horng-Huei Tseng
IPC分类号： H01L29/40 , H01L23/52 , H01L21/4763 , H01L23/522 , H01L23/485 , H01L23/532 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76811 , H01L21/76813 , H01L21/76831 , H01L23/485 , H01L23/5329
摘要： An interconnection structure includes a non-insulator structure, a liner layer, a dielectric structure and a conductive structure. The liner layer is present on the non-insulator structure and has an opening therein. The dielectric structure is present on the liner layer. The dielectric structure includes a via opening therein. The conductive structure is present in the via opening of the dielectric structure and electrically connected to the non-insulator structure through the opening of the liner layer. At least a portion of the conductive structure tapers along a direction from the non-insulator structure to the dielectric structure.

7. 发明授权

US10032774B2 Semiconductor device and manufacture method thereof 有权
公开(公告)号：US10032774B2
公开(公告)日：2018-07-24
申请号：US15722229
申请日：2017-10-02
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
发明人： Che-Cheng Chang , Chih-Han Lin , Horng-Huei Tseng
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/51 , H01L29/06 , H01L29/66 , H01L29/49
摘要： A semiconductor device includes a semiconductor substrate and at least one gate stack. The gate stack is present on the semiconductor substrate, and the gate stack includes at least one work function conductor and a filling conductor. The work function conductor has a recess therein. The filling conductor includes a plug portion and a cap portion. The plug portion is present in the recess of the work function conductor. The cap portion caps the work function conductor.

8. 发明申请

US20140264589A1 SEMICONDUCTOR STRUCTURE PROFILE 有权
标题翻译：半导体结构简档
公开(公告)号：US20140264589A1
公开(公告)日：2014-09-18
申请号：US13799227
申请日：2013-03-13
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Che-Cheng Chang , Jr-Jung Lin , Yi - Jen Chen , Yung Jung Chang
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7833 , H01L21/26586 , H01L21/28158 , H01L29/42364 , H01L29/513 , H01L29/66545 , H01L29/6659
摘要： One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. In some embodiments, a semiconductor structure includes a substrate, a first lightly doped drain (LDD), a second LDD, an interface layer (IL), a high-k stack, a gate region, a dummy poly region, a first hard mask (HM) region, a second HM region, and a seal spacer region. The HK stack has a HK stack width and the gate region has a gate region width that is less than or substantially equal to the HK stack width. Because of the increased width of the HK stack, some of the HK stack likely overlaps some of the first LDD or the second LDD. In this manner, a saturation current and a threshold voltage associated with the semiconductor structure are improved. The increased width of the HK stack also protects more of the IL during LDD implanting.
摘要翻译：本文提供了用于形成半导体结构的技术或系统的一个或多个实施例。在一些实施例中，半导体结构包括衬底，第一轻掺杂漏极（LDD），第二LDD，界面层（IL），高k堆叠，栅极区域，虚拟多晶硅区域，第一硬掩模（HM）区域，第二HM区域和密封间隔区域。 HK堆栈具有HK堆叠宽度，并且栅极区域具有小于或基本上等于HK堆叠宽度的栅极区域宽度。由于香港堆栈的宽度有所增加，部分香港堆栈可能会重叠部分第一LDD或第二LDD。以这种方式，提高了与半导体结构相关联的饱和电流和阈值电压。在LDD植入期间，HK堆叠的宽度增加也可以保护更多的IL。

9. 发明授权

US11411001B2 Integrated circuit and manufacturing method thereof 有权
公开(公告)号：US11411001B2
公开(公告)日：2022-08-09
申请号：US17007127
申请日：2020-08-31
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
发明人： Che-Cheng Chang , Chih-Han Lin , Horng-Huei Tseng
IPC分类号： H01L27/092 , H01L29/423 , H01L29/66 , H01L29/78 , H01L21/8238 , H01L21/3215 , H01L21/28
摘要： An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor device is present on the substrate. The n-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle. The p-type semiconductor device is present on the substrate. The p-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.

10. 发明授权

US10510752B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US10510752B2
公开(公告)日：2019-12-17
申请号：US15729987
申请日：2017-10-11
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
发明人： Che-Cheng Chang , Chih-Han Lin
IPC分类号： H01L29/06 , H01L29/08 , H01L29/66 , H01L29/78 , H01L21/306 , H01L27/088 , H01L29/423
摘要： A semiconductor device includes at least one semiconductor fin, a gate electrode, at least one gate spacer, and a gate dielectric. The semiconductor fin includes at least one recessed portion and at least one channel portion. The gate electrode is present on at least the channel portion of the semiconductor fin. The gate spacer is present on at least one sidewall of the gate electrode. The gate dielectric is present at least between the channel portion of the semiconductor fin and the gate electrode. The gate dielectric extends farther than at least one end surface of the channel portion of the semiconductor fin.

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