专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09081293B2 System and method for lithography exposure with correction of overlay shift induced by mask heating 有权
标题翻译：用于光刻曝光的系统和方法，通过掩模加热引起的覆盖位移校正
公开(公告)号：US09081293B2
公开(公告)日：2015-07-14
申请号：US14056576
申请日：2013-10-17
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Dong-Hsu Cheng , Chun-Jen Chen , Ming-Ho Tsai , Jim Liang , Yung-Hsiang Chen , Jun-Hua Chen
IPC分类号： G06F17/50 , G03F1/70 , G03F7/00
CPC分类号： G03F7/70875 , G03F1/70 , G03F7/00 , G03F7/70633 , G03F7/70783
摘要： A method of exposing a wafer substrate includes receiving an integrated circuit (IC) design layout defining a pattern; determining a temperature profile of a mask based on the IC design layout, the pattern being formed on the mask; calculating a pre-corrected overlay shift for the mask based on the calculated temperature profile; and exposing a resist layer coated on a substrate using the mask with overlay compensation based on the pre-corrected overlay shift.
摘要翻译：暴露晶片衬底的方法包括接收限定图案的集成电路（IC）设计布局; 基于所述IC设计布局确定掩模的温度分布，所述图案形成在所述掩模上; 基于所计算的温度分布计算所述掩模的预校正覆盖移位; 以及使用所述掩模将涂覆在基板上的抗蚀剂层基于预校正的覆盖层移位进行覆盖补偿。

2. 发明授权

US11469198B2 Semiconductor device manufacturing method and associated semiconductor die 有权
公开(公告)号：US11469198B2
公开(公告)日：2022-10-11
申请号：US16353425
申请日：2019-03-14
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Ming-Ho Tsai , Jyun-Hong Chen , Chun-Chen Liu , Yu-Nu Hsu , Peng-Ren Chen , Wen-Hao Cheng , Chi-Ming Tsai
IPC分类号： H01L23/48 , H01L23/00
摘要： A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.

3. 发明授权

US09230867B2 Structure and method for E-beam in-chip overlay mark 有权
标题翻译：电子束片内重叠标记的结构和方法
公开(公告)号：US09230867B2
公开(公告)日：2016-01-05
申请号：US14286433
申请日：2014-05-23
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Dong-Hsu Cheng , Ming-Ho Tsai , Chih-Chung Huang , Yung-Hsiang Chen , Jyun-Hong Chen
IPC分类号： H01L21/00 , H01L21/66 , G03F7/20
CPC分类号： H01L22/12 , G03F7/70633
摘要： The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.
摘要翻译：本公开提供了一种集成电路结构，其包括具有第一区域的半导体衬底和具有小于约10微米×10微米的面积的第二区域; 半导体衬底上的第一材料层，并被图案化以具有第一区域中的第一电路特征和第二区域中的第一标记; 以及在所述第一材料层之上的第二材料层，并被图案化以具有所述第一区域中的第二电路特征和所述第二区域中的第二标记。第一标记包括沿第一方向定向的第一标记特征，以及在垂直于第一方向的第二方向上定向的第二标记特征。第二标记包括沿第一方向定向的第三标记特征，第四标记特征指向第二方向。

4. 发明申请

US20150316861A1 System and Method for Lithography Exposure With Correction of Overlay Shift Induced By Mask Heating 审中-公开
标题翻译：用于通过掩模加热引起的覆盖移位校正的光刻曝光的系统和方法
公开(公告)号：US20150316861A1
公开(公告)日：2015-11-05
申请号：US14798783
申请日：2015-07-14
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Dong-Hsu Cheng , Chun-Jen Chen , Jim Liang , Yung-Hsiang Chen , Jun-Hua Chen , Ming-Ho Tsai
IPC分类号： G03F7/20
CPC分类号： G03F7/70875 , G03F1/70 , G03F7/00 , G03F7/70633 , G03F7/70783
摘要： A method of exposing a wafer substrate includes receiving an integrated circuit (IC) design layout defining a pattern; determining a temperature profile of a mask based on the IC design layout, the pattern being formed on the mask; calculating a pre-corrected overlay shift for the mask based on the calculated temperature profile; and exposing a resist layer coated on a substrate using the mask with overlay compensation based on the pre-corrected overlay shift.
摘要翻译：暴露晶片衬底的方法包括接收限定图案的集成电路（IC）设计布局; 基于所述IC设计布局确定掩模的温度分布，所述图案形成在所述掩模上; 基于所计算的温度分布计算所述掩模的预校正覆盖移位; 以及使用所述掩模将涂覆在基板上的抗蚀剂层基于预校正的覆盖层移位进行覆盖补偿。

5. 发明申请

US20140272717A1 System and Method for Lithography Exposure with Correction of Overlay Shift Induced by Mask Heating 有权
标题翻译：用于通过掩模加热引起的覆盖移位校正的光刻曝光的系统和方法
公开(公告)号：US20140272717A1
公开(公告)日：2014-09-18
申请号：US14056576
申请日：2013-10-17
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Dong-Hsu Cheng , Chun-Jen Chen , Ming-Ho Tsai , Jim Liang , Yung-Hsiang Chen , Jun-Hua Chen
IPC分类号： G03F1/70 , G06F17/50
CPC分类号： G03F7/70875 , G03F1/70 , G03F7/00 , G03F7/70633 , G03F7/70783
摘要： A method of exposing a wafer substrate includes receiving an integrated circuit (IC) design layout defining a pattern; determining a temperature profile of a mask based on the IC design layout, the pattern being formed on the mask; calculating a pre-corrected overlay shift for the mask based on the calculated temperature profile; and exposing a resist layer coated on a substrate using the mask with overlay compensation based on the pre-corrected overlay shift.
摘要翻译：暴露晶片衬底的方法包括接收限定图案的集成电路（IC）设计布局; 基于所述IC设计布局确定掩模的温度分布，所述图案形成在所述掩模上; 基于所计算的温度分布计算所述掩模的预校正覆盖移位; 以及使用所述掩模将涂覆在基板上的抗蚀剂层基于预校正的覆盖层移位进行覆盖补偿。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式