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1. 发明申请

US20180061986A1 Structure and Method for Integrated Circuit 审中-公开
公开(公告)号：US20180061986A1
公开(公告)日：2018-03-01
申请号：US15803238
申请日：2017-11-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shin-Jiun Kuang , Tsung-Hsing Yu , Yi-Ming Sheu
IPC分类号： H01L29/78 , H01L29/66 , H01L29/267 , H01L21/8238 , H01L29/08 , H01L27/092 , H01L29/165
摘要： The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.

2. 发明授权

US09831341B2 Structure and method for integrated circuit 有权
公开(公告)号：US09831341B2
公开(公告)日：2017-11-28
申请号：US14305416
申请日：2014-06-16
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shin-Jiun Kuang , Tsung-Hsing Yu , Yi-Ming Sheu
IPC分类号： H01L29/78 , H01L21/82 , H01L27/092 , H01L29/08 , H01L21/8238 , H01L29/267 , H01L29/66 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/823814 , H01L21/823864 , H01L27/092 , H01L29/0847 , H01L29/165 , H01L29/267 , H01L29/6653 , H01L29/66636
摘要： The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.

3. 发明授权

US09893183B2 Semiconductor structure and manufacturing method thereof 有权
公开(公告)号：US09893183B2
公开(公告)日：2018-02-13
申请号：US14328061
申请日：2014-07-10
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Shin-Jiun Kuang , Tsung-Hsing Yu , Yi-Ming Sheu
IPC分类号： H01L29/78 , H01L29/08 , H01L21/02 , H01L29/66 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/0243 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L29/0847 , H01L29/165 , H01L29/66628 , H01L29/66636
摘要： Some embodiments of the present disclosure provide a semiconductor structure including a substrate and an epitaxy region partially disposed in the substrate. The epitaxy region includes a substance with a lattice constant that is larger than a lattice constant of the substrate. The concentration profile of a substance in the epitaxy region is monotonically increasing from a bottom portion of the epitaxy region to a of the epitaxy region. A first layer of the epitaxy region has a height to width ratio of about 2. The first layer is a layer positioned closest to the substrate, and the first layer has an average concentration of the substance from about 20 to about 32 percent. A second layer disposed over the first layer. The second layer has a bottom portion with a concentration of the substance from about 27 percent to about 37 percent.

4. 发明授权

US09281372B2 Metal gate structure and manufacturing method thereof 有权
标题翻译：金属栅结构及其制造方法
公开(公告)号：US09281372B2
公开(公告)日：2016-03-08
申请号：US14334004
申请日：2014-07-17
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Shin-Jiun Kuang , Tsung-Hsing Yu , Yi-Ming Sheu , Chun-Yi Lee
IPC分类号： H01L29/00 , H01L21/00 , H01L29/49 , H01L29/51 , H01L21/28
CPC分类号： H01L29/4983 , H01L21/28088
摘要： The present disclosure provides a semiconductor structure includes a gate structure disposed over a substrate, wherein the gate structure includes a high-k dielectric layer and a work function structure. The high-k dielectric layer includes a base portion and a side portion, the side portion is extended from an end of the base portion, the side portion is substantially orthogonal to the base portion. The work function structure includes a first metal disposed over the high-k dielectric layer and a second metal disposed over the first metal and including a bottom portion and a sidewall portion extended from an end of the bottom portion, wherein the first metal includes different materials from the second metal, and a length of an interface between the sidewall portion and the bottom portion to a length of the bottom portion within the high-k dielectric layer is in a predetermined ratio.
摘要翻译：本公开提供了一种半导体结构，包括设置在衬底上的栅极结构，其中栅极结构包括高k电介质层和功函数结构。高k电介质层包括基部和侧部，侧部从基部的端部延伸，侧部大致垂直于基部。工作功能结构包括设置在高k电介质层上的第一金属和设置在第一金属上的第二金属，并且包括底部和从底部的端部延伸的侧壁部分，其中第一金属包括不同的材料并且在高k电介质层内的侧壁部分和底部部分之间的接合长度与底部部分的长度成一定比例。

5. 发明授权

US11502198B2 Structure and method for integrated circuit 有权
公开(公告)号：US11502198B2
公开(公告)日：2022-11-15
申请号：US16983833
申请日：2020-08-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shin-Jiun Kuang , Tsung-Hsing Yu , Yi-Ming Sheu
IPC分类号： H01L31/119 , H01L29/78 , H01L29/08 , H01L21/8238 , H01L29/267 , H01L29/66 , H01L29/165 , H01L27/092
摘要： The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.

6. 发明申请

US20210305426A1 Structure and Method for Integrated Circuit 有权
公开(公告)号：US20210305426A1
公开(公告)日：2021-09-30
申请号：US17235057
申请日：2021-04-20
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shin-Jiun Kuang , Tsung-Hsing Yu , Yi-Ming Sheu
IPC分类号： H01L29/78 , H01L29/08 , H01L21/8238 , H01L29/267 , H01L29/66 , H01L29/165 , H01L27/092
摘要： The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.

7. 发明授权

US11004955B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US11004955B2
公开(公告)日：2021-05-11
申请号：US16730495
申请日：2019-12-30
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Shin-Jiun Kuang , Yi-Han Wang , Tsung-Hsing Yu , Yi-Ming Sheu
IPC分类号： H01L29/417 , H01L29/78 , H01L29/267 , H01L29/165 , H01L29/66
摘要： A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.

8. 发明授权

US10741688B2 Structure and method for integrated circuit 有权
公开(公告)号：US10741688B2
公开(公告)日：2020-08-11
申请号：US15803238
申请日：2017-11-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shin-Jiun Kuang , Tsung-Hsing Yu , Yi-Ming Sheu
IPC分类号： H01L29/78 , H01L29/08 , H01L21/8238 , H01L29/267 , H01L29/66 , H01L27/092 , H01L29/165
摘要： The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.

9. 发明授权

US10522657B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US10522657B2
公开(公告)日：2019-12-31
申请号：US16138462
申请日：2018-09-21
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Shin-Jiun Kuang , Yi-Han Wang , Tsung-Hsing Yu , Yi-Ming Sheu
IPC分类号： H01L29/417 , H01L21/8238 , H01L29/165 , H01L29/16 , H01L29/08 , H01L21/768 , H01L21/8234 , H01L29/66 , H01L29/78
摘要： A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.

10. 发明授权

US09502253B2 Method of manufacturing an integrated circuit 有权
标题翻译：集成电路的制造方法
公开(公告)号：US09502253B2
公开(公告)日：2016-11-22
申请号：US14490177
申请日：2014-09-18
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Zhiqiang Wu , Yi-Ming Sheu , Tsung-Hsing Yu , Kuan-Lun Cheng , Chih-Pin Tsao , Wen-Yuan Chen , Chun-Fu Cheng , Chih-Ching Wang
IPC分类号： H01L21/265 , H01L21/8234 , H01L29/66
CPC分类号： H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823468 , H01L29/66492 , H01L29/66545 , H01L29/66575
摘要： A method of forming an integrated circuit comprises forming a first doped region in a substrate using a first angle ion implantation performed on a first side of a gate structure. The gate structure has a length in a first direction and a width in a second direction. The method also comprises forming a second doped region in the substrate using a second angle ion implantation performed on a second side of the gate structure. The first angle ion implantation has a first implantation angle with respect to the second direction and the second angle ion implantation has a second implantation angle with respect to the second direction. Each of the first implantation angle and the second implantation angle is substantially larger than 0° and less than 90°.
摘要翻译：形成集成电路的方法包括使用在栅极结构的第一侧上进行的第一角度离子注入在衬底中形成第一掺杂区域。栅极结构具有在第一方向上的长度和在第二方向上的宽度。该方法还包括使用在栅极结构的第二侧上执行的第二角度离子注入在衬底中形成第二掺杂区域。第一角度离子注入相对于第二方向具有第一注入角度，而第二角度离子注入相对于第二方向具有第二注入角度。第一植入角度和第二植入角度中的每一个基本上大于0°且小于90°。

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