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1. 发明授权

US10600495B2 Parallel memory self-testing 有权
公开(公告)号：US10600495B2
公开(公告)日：2020-03-24
申请号：US15891789
申请日：2018-02-08
申请人： Texas Instruments Incorporated
发明人： Devanathan Varadarajan , Sumant Kale
IPC分类号： G11C29/38 , G11C29/26 , G11C29/36
摘要： In described examples of circuitry and methods for testing multiple memories, a controller generates a sequence of commands to be applied to one or more of the memories, where each given command includes expected data, and a command address. Local adapters are individually coupled with the controller and with an associated memory. Each local adapter translates the command to a memory type of the associated memory, maps the command address to a local address of the associated memory, and provides test results to the controller according to read data from the local address of the associated memory and the expected data of the command.

2. 发明申请

US20190156908A1 ENABLING HIGH AT-SPEED TEST COVERAGE OF FUNCTIONAL MEMORY INTERFACE LOGIC BY SELECTIVE USAGE OF TEST PATHS 审中-公开
公开(公告)号：US20190156908A1
公开(公告)日：2019-05-23
申请号：US16192796
申请日：2018-11-15
申请人： Texas Instruments Incorporated
发明人： Devanathan Varadarajan , Lei Wu
IPC分类号： G11C29/16 , G11C29/10 , G11C29/12 , G11C29/32 , G01R31/3185
摘要： A device to test functional memory interface logic of a core under test is described herein. The device includes and utilizes a built in self test controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at built in self test mode, an at-speed functional mode is utilized to capture a desired memory output.

3. 发明授权

US11568951B2 Screening of memory circuits 有权
公开(公告)号：US11568951B2
公开(公告)日：2023-01-31
申请号：US16817096
申请日：2020-03-12
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Francisco Adolfo Cano , Devanathan Varadarajan , Anthony Martin Hill
IPC分类号： G11C29/00 , G11C29/38 , G11C29/50 , G11C11/419 , G11C11/418 , G11C11/412
摘要： Systems and methods of screening memory cells by modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven as compared to a nominal operating voltage on the wordline. In a write operation, the one or both of the bitline and wordline may be overdriven or underdriven as compared to a nominal operating voltage of each. A built-in self test (BIST) system for screening a memory array has bitline and wordline margin controls to modulate bitline and wordline voltage, respectively, in the memory array.

4. 发明授权

US11436090B2 Non-volatile memory compression for memory repair 有权
公开(公告)号：US11436090B2
公开(公告)日：2022-09-06
申请号：US17125244
申请日：2020-12-17
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Devanathan Varadarajan , Ramakrishnan Venkatasubramanian , Varun Singh
IPC分类号： G06F11/14 , H03M7/30
摘要： One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.

5. 发明授权

US09053799B2 Optimizing fuseROM usage for memory repair 有权
标题翻译：优化fuseROM用于内存修复
公开(公告)号：US09053799B2
公开(公告)日：2015-06-09
申请号：US14038306
申请日：2013-09-26
申请人： Texas Instruments Incorporated
发明人： Devanathan Varadarajan , Harsharaj Ellur
IPC分类号： G11C29/00 , G11C17/16 , G11C17/18 , G11C29/44
CPC分类号： G11C29/4401 , G11C17/16 , G11C17/18 , G11C29/38 , G11C29/785 , G11C29/789 , G11C2029/4402
摘要： A memory repair system in an integrated circuit (IC) that optimizes the fuseROM used for memory repair. The IC includes a plurality of memory wrappers. Each memory wrapper includes a memory block with a fuse register and a bypass register. The bypass register has a bypass data that indicates a defective memory wrapper of the plurality of memory wrappers. A fuseROM controller is coupled to the plurality of memory wrappers. A memory bypass chain links the bypass registers in the plurality of memory wrappers with the fuseROM controller. The fuseROM controller loads the bypass data in the memory bypass chain. A memory data chain links the fuse registers in the plurality of memory wrappers with the fuseROM controller. The memory data chain is re-configured to link the fuse registers in a set of defective memory wrappers of the plurality of memory wrappers responsive to the bypass data loaded in the memory bypass chain.
摘要翻译：集成电路（IC）中的存储器修复系统，其优化用于存储器修复的熔丝ROM。 IC包括多个存储器包装器。每个存储器包装器包括具有熔丝寄存器和旁路寄存器的存储器块。旁路寄存器具有指示多个存储器包装器的有缺陷的存储器包装器的旁路数据。熔丝ROM控制器耦合到多个存储器包装器。存储器旁路链将多个存储器封装器中的旁路寄存器与熔丝ROM控制器链接。 fuseROM控制器将旁路数据加载到内存旁路链中。存储器数据链将多个存储器包装器中的熔丝寄存器与熔丝ROM控制器链接。存储器数据链被重新配置为响应于加载在存储器旁路链中的旁路数据，将多个存储器包装器中的一组缺陷存储器包装器中的熔丝寄存器链接。

6. 发明申请

US20170184662A1 Centralized Built-In Soft-Repair Architecture for Integrated Circuits With Embedded Memories 审中-公开
公开(公告)号：US20170184662A1
公开(公告)日：2017-06-29
申请号：US15275694
申请日：2016-09-26
申请人： Texas Instruments Incorporated
发明人： Devanathan Varadarajan , Sumant Dinkar Kale
IPC分类号： G01R31/28 , G06F11/20 , G11C29/12
CPC分类号： G11C29/4401 , G01R31/2851 , G06F11/2017 , G11C29/12 , G11C29/44 , G11C29/70 , G11C29/702 , G11C29/72 , G11C29/787 , G11C29/838 , G11C2029/0401
摘要： A large-scale integrated circuit with built-in self-repair (BISR) circuitry for enabling redundancy repair for embedded memories in each of a plurality of processor cores with embedded built-in self-test (BIST) circuitry. The BISR circuitry receives and decodes BIST data from the embedded memories into fail signature data in a physical-aware form on which repair analysis can be performed. The fail signature data is reformatted into a unified repair format, such that a fuse encoder circuit can be used to encode fuse patterns in that unified repair format for a repair entity for each of the embedded memories. The fuse patterns are reconfigured into the appropriate order for storing in shadow fuse registers associated with the specific embedded memories.

7. 发明申请

US20140189450A1 Hierarchical, Distributed Built-in Self-Repair Solution 有权
标题翻译：分层式，分布式内置自修复解决方案
公开(公告)号：US20140189450A1
公开(公告)日：2014-07-03
申请号：US14108489
申请日：2013-12-17
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Devanathan Varadarajan , Raghavendra Prasad KS , Harsharaj Ellur
IPC分类号： G11C29/12
CPC分类号： G11C29/4401 , G11C29/785 , G11C2029/0409 , G11C2029/4402
摘要： A built-in self-test (BIST) circuit to test one or more memory blocks on an integrated circuit. The one or more memory blocks further includes a first memory block and a second memory block A built-in soft-repair controller (BISoR) is provided to soft repair the one or more memory blocks. The BIST circuit in conjunction with the BISoR is configured to test and soft repair the first memory block before performing test and soft repair of the second memory block.
摘要翻译：内置自检（BIST）电路，用于测试集成电路上的一个或多个存储器块。一个或多个存储器块还包括第一存储器块和第二存储器块A，提供内置的软修复控制器（BISoR）来软件修复所述一个或多个存储器块。配置BISoR的BIST电路配置为在执行第二个内存块的测试和软修复之前测试和软修复第一个内存块。

8. 发明授权

US11631472B2 Built-in memory repair with repair code compression 有权
公开(公告)号：US11631472B2
公开(公告)日：2023-04-18
申请号：US17125323
申请日：2020-12-17
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Devanathan Varadarajan , Varun Singh
IPC分类号： G11C29/16 , G11C29/44 , G11C29/40
摘要： In a described example, an integrated circuit (IC) includes a repairable memory system. A repair controller is coupled to the repairable memory system. The repair controller includes compression logic configured to encode memory repair code data for a respective instance of the repairable memory system and provide compressed repair data. A non-volatile memory controller is coupled to the repair controller and to non-volatile memory. The non-volatile memory controller is configured to transfer the compressed repair data to the non-volatile memory for storage.

9. 发明申请

US20220413966A1 NON-VOLATILE MEMORY COMPRESSION FOR MEMORY REPAIR 有权
公开(公告)号：US20220413966A1
公开(公告)日：2022-12-29
申请号：US17901337
申请日：2022-09-01
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Devanathan Varadarajan , Ramakrishnan Venkatasubramanian , Varun Singh
IPC分类号： G06F11/14 , H03M7/30
摘要： One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.

10. 发明申请

US20210327525A1 AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES 有权
公开(公告)号：US20210327525A1
公开(公告)日：2021-10-21
申请号：US17364647
申请日：2021-06-30
申请人： Texas Instruments Incorporated
发明人： Devanathan Varadarajan , Lei Wu
IPC分类号： G11C29/16 , G11C29/10 , G01R31/3185 , G11C29/32 , G11C29/12 , G11C29/26 , G11C29/02 , G11C29/14 , G11C29/36
摘要： A device to test functional memory interface logic of a core under test is described herein. The device includes and utilizes a built in self test controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at built in self test mode, an at-speed functional mode is utilized to capture a desired memory output.

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