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1. 发明授权

US10832911B2 Semiconductor device 有权
公开(公告)号：US10832911B2
公开(公告)日：2020-11-10
申请号：US16555960
申请日：2019-08-29
申请人： TOYODA GOSEI CO., LTD.
发明人： Nariaki Tanaka , Toru Oka , Yukihisa Ueno , Kota Yasunishi
IPC分类号： H01L21/04 , H01L29/87 , H01L21/02 , H01L29/872 , H01L29/47 , H01L21/225 , H01L29/20
摘要： An n-type GaN layer, a p-type diffusion region formed by ion implantation and annealing in a part of the n-type layer, and a Schottky electrode are formed on the n-type layer. A region without the p-type region is defined as region A, and a region with the p-type region is defined as region B. In region A, an average density of each electron trap level of the n-type layer in a region having a depth of 0.8 μm to 1.6 μm on the n-type layer side is set so as to satisfy the predetermined conditions. In region B, an average density of each carrier trap level of the n-type layer in a region having a depth of 0.8 μm to 1.6 μm on the n-type layer side from a boundary between the n-type layer and the p-type diffusion region is set so as to satisfy the predetermined conditions.

2. 发明授权

US10777674B2 Semiconductor device 有权
公开(公告)号：US10777674B2
公开(公告)日：2020-09-15
申请号：US16351930
申请日：2019-03-13
申请人： TOYODA GOSEI CO., LTD.
发明人： Takaki Niwa , Toru Oka
IPC分类号： H01L29/15 , H01L31/0256 , H01L29/78 , H01L29/20 , H01L29/417 , H01L29/10
摘要： To suppress breakage of a diode. A semiconductor device comprises a stacked body and a first electrode. The stacked body includes a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, and a fourth nitride semiconductor layer that are stacked in sequence. The first electrode is in contact with a surface of the first nitride semiconductor layer that is opposite to a surface in contact with the second nitride semiconductor layer. The semiconductor device includes a transistor forming region and a diode forming region adjacent to the transistor forming region. The transistor forming region includes a first groove, a second electrode, and a third electrode. The first groove has a bottom portion located in the second nitride semiconductor layer. The second electrode is formed on a surface of the first groove. The third electrode is in contact with a surface of the fourth nitride semiconductor layer that is opposite to a surface in contact with the third nitride semiconductor layer. The diode forming region includes a second groove and a Schottky electrode. The second groove has a bottom portion located in the third nitride semiconductor layer. The Schottky electrode makes a Schottky barrier junction with the third nitride semiconductor layer and is electrically connected to the third electrode.

3. 发明授权

US08987077B2 Group III nitride semiconductor device, production method therefor, and power converter 有权
标题翻译： III族氮化物半导体器件及其制造方法和功率转换器
公开(公告)号：US08987077B2
公开(公告)日：2015-03-24
申请号：US14011573
申请日：2013-08-27
申请人： Toyoda Gosei Co., Ltd.
发明人： Toru Oka
IPC分类号： H01L21/336 , H01L29/66 , H01L29/778 , H01L29/861 , H01L23/29 , H01L23/31 , H01L29/20 , H01L29/40 , H01L29/423
CPC分类号： H01L29/66462 , H01L23/291 , H01L23/3171 , H01L29/2003 , H01L29/407 , H01L29/4236 , H01L29/7785 , H01L29/7787 , H01L29/861 , H01L2924/0002 , H01L2924/00
摘要： A method for producing a semiconductor device, includes forming a first carrier transport layer including a Group III nitride semiconductor, forming a mask on a region of the first carrier transport layer, selectively re-growing a second carrier transport layer on an unmasked region of the first carrier transport layer, the second carrier transport layer including a Group III nitride semiconductor, and selectively growing a carrier supply layer on the second carrier transport layer, the carrier supply layer including a Group III nitride semiconductor having a bandgap different from that of the Group III nitride semiconductor of the second carrier transport layer.
摘要翻译：一种制造半导体器件的方法，包括：形成第一载流子传输层，其包括III族氮化物半导体，在第一载流子传输层的区域上形成掩模，在第一载流子迁移层的未掩蔽区上选择性地再生长第二载流子传输层; 第一载流子传输层，所述第二载流子传输层包括III族氮化物半导体，并且在所述第二载流子传输层上选择性地生长载流子供应层，所述载流子供应层包括具有不同于所述基团的带隙的III族氮化物半导体 III族氮化物半导体。

4. 发明申请

US20140319686A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140319686A1
公开(公告)日：2014-10-30
申请号：US14263877
申请日：2014-04-28
申请人： TOYODA GOSEI CO., LTD.
发明人： Noriaki Murakami , Toru Oka
IPC分类号： H01L21/768 , H01L23/498
CPC分类号： H01L23/4827 , H01L21/28575 , H01L29/2003 , H01L29/452 , H01L29/475 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： An object is to use an electrode made of a less expensive material than gold (Au). A semiconductor device comprises: a first titanium layer that is formed to cover at least part of a semiconductor layer and is made of titanium; an aluminum layer that is formed on the first titanium layer on opposite side of the semiconductor layer and mainly consists of aluminum; a titanium nitride layer that is formed on the aluminum layer on opposite side of the first titanium layer and is made of titanium nitride; and an electrode layer that is formed on the titanium nitride layer on opposite side of the aluminum layer and is made of silver.
摘要翻译：目的是使用由金（Au）成本较低的材料制成的电极。半导体器件包括：形成为覆盖半导体层的至少一部分并由钛制成的第一钛层; 铝层，其形成在半导体层的相对侧上的第一钛层上，主要由铝构成; 氮化钛层，形成在第一钛层的相反侧的铝层上，并由氮化钛制成; 以及形成在铝层相反侧的氮化钛层上并由银制成的电极层。

5. 发明授权

US10854454B2 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US10854454B2
公开(公告)日：2020-12-01
申请号：US16390151
申请日：2019-04-22
申请人： TOYODA GOSEI CO., LTD.
发明人： Yukihisa Ueno , Nariaki Tanaka , Junya Nishii , Toru Oka
IPC分类号： H01L29/66 , H01L21/265 , H01L29/423 , H01L29/78
摘要： To restrain a side portion of a trench from being damaged by ion implantation. A method for manufacturing a semiconductor device comprises a stacking process, an ion implantation process, a heat treatment process, a groove forming process, and a first electrode forming process. In the stacking process, a p-type semiconductor layer is stacked on a first n-type semiconductor layer. In the ion implantation process, an n-type impurity or a p-type impurity is ion-implanted into a position on a surface of the p-type semiconductor layer. The position is away from a position where a groove is to be formed. In the heat treatment process, heat treatment is performed to activate the ion-implanted impurity so as to form an implanted region and to diffuse a p-type impurity in the p-type semiconductor layer into the first n-type semiconductor layer located below the implanted region so as to form a p-type impurity diffused region. In the groove forming process, the groove that penetrates the p-type semiconductor layer and has a bottom portion located in the first n-type semiconductor layer is formed. In the first electrode forming process, the first electrode is formed on an insulation film on a surface of the groove.

6. 发明授权

US09331157B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09331157B2
公开(公告)日：2016-05-03
申请号：US14104962
申请日：2013-12-12
申请人： TOYODA GOSEI CO., LTD.
发明人： Toru Oka , Nariaki Tanaka
IPC分类号： H01L21/00 , H01L29/417 , H01L29/78 , H01L29/45 , H01L29/66 , H01L21/04 , H01L21/285 , H01L29/16 , H01L29/20
CPC分类号： H01L29/41741 , H01L21/0485 , H01L21/28575 , H01L29/1608 , H01L29/2003 , H01L29/45 , H01L29/452 , H01L29/66068 , H01L29/66727 , H01L29/66734 , H01L29/7802 , H01L29/7813
摘要： A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer connected with the p-type semiconductor layer; a first electrode layer formed on the n-type semiconductor layer; and a second electrode layer formed on the p-type semiconductor layer. The first electrode layer and the second electrode layer are electrically connected such as to each operate at an identical potential. The first electrode layer is connected with a connection line which is a part of a peripheral line of a joint interface between the p-type semiconductor layer and the n-type semiconductor layer on an interface side between the second electrode layer and the p-type semiconductor layer, with a surface of the p-type semiconductor layer and with at least a part of a surface of the second electrode layer which is opposite to a surface of the second electrode layer that is in contact with the p-type semiconductor layer.
摘要翻译：半导体器件包括：p型半导体层; 与p型半导体层连接的n型半导体层; 形成在所述n型半导体层上的第一电极层; 以及形成在p型半导体层上的第二电极层。第一电极层和第二电极层电连接，以使其各自以相同的电位工作。第一电极层与作为p型半导体层和n型半导体层之间的接合界面的外围线的一部分的连接线连接在第二电极层和p型之间的界面侧半导体层，其具有p型半导体层的表面和与第二电极层的与p型半导体层接触的表面相对的第二电极层的表面的至少一部分。

7. 发明授权

US09136367B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09136367B2
公开(公告)日：2015-09-15
申请号：US14323159
申请日：2014-07-03
申请人： TOYODA GOSEI CO., LTD.
发明人： Yukihisa Ueno , Toru Oka , Kazuya Hasegawa
IPC分类号： H01L27/04 , H01L29/78 , H01L21/28 , H01L29/20 , H01L29/06 , H01L29/66 , H01L23/31
CPC分类号： H01L29/78 , H01L21/28264 , H01L21/31133 , H01L23/3178 , H01L23/3192 , H01L29/0692 , H01L29/2003 , H01L29/4236 , H01L29/513 , H01L29/66143 , H01L29/66522 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a p-type semiconductor layer mainly made of GaN; an n-type semiconductor layer mainly made of GaN and joined with the p-type semiconductor layer; a protective film arranged to coat the p-type semiconductor layer and the n-type semiconductor layer; a gate insulating film arranged to coat the p-type semiconductor layer and the n-type semiconductor layer; and a gate electrode joined with the gate insulating film. The protective film includes: a first layer made of Al2O3 and arranged adjacent to the p-type semiconductor layer and the n-type semiconductor layer to coat an edge of a p-n junction surface; a second layer made of an electrical insulation material different from Al2O3 and formed on the first layer; and an opening structure formed to pass through the first layer and the second layer. The gate insulating film is placed inside of the opening structure.
摘要翻译：半导体器件包括：主要由GaN制成的p型半导体层; 主要由GaN制成并与p型半导体层接合的n型半导体层; 布置成涂覆p型半导体层和n型半导体层的保护膜; 布置成涂覆p型半导体层和n型半导体层的栅极绝缘膜; 以及与栅极绝缘膜接合的栅电极。保护膜包括：由Al 2 O 3制成的第一层，并且邻近p型半导体层和n型半导体层布置以覆盖p-n结表面的边缘; 由与Al2O3不同的电绝缘材料制成的第二层，形成在第一层上; 以及形成为穿过第一层和第二层的开口结构。栅极绝缘膜放置在开口结构内部。

8. 发明授权

US09123635B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US09123635B2
公开(公告)日：2015-09-01
申请号：US14105018
申请日：2013-12-12
申请人： TOYODA GOSEI CO., LTD.
发明人： Toru Oka , Nariaki Tanaka
IPC分类号： H01L21/28 , H01L31/072 , H01L29/20 , H01L21/285 , H01L29/45
CPC分类号： H01L29/2003 , H01L21/28587 , H01L29/401 , H01L29/41741 , H01L29/41766 , H01L29/452 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A manufacturing method of a semiconductor device includes the steps of: forming a first electrode layer on a n-type semiconductor layer; forming a second electrode layer on a p-type semiconductor layer; and performing heat treatment for the first electrode layer and the second electrode layer formed on the semiconductor layers. Temperature of the heat treatment is not lower than 400 degrees centigrade and not higher than 650 degrees centigrade.
摘要翻译：半导体器件的制造方法包括以下步骤：在n型半导体层上形成第一电极层; 在p型半导体层上形成第二电极层; 对形成在半导体层上的第一电极层和第二电极层进行热处理。热处理温度不低于400摄氏度，不高于650摄氏度。

9. 发明申请

US20140167062A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20140167062A1
公开(公告)日：2014-06-19
申请号：US14105018
申请日：2013-12-12
申请人： TOYODA GOSEI CO., LTD.
发明人： Toru Oka , NARIAKI TANAKA
IPC分类号： H01L21/283 , H01L29/20 , H01L29/45
CPC分类号： H01L29/2003 , H01L21/28587 , H01L29/401 , H01L29/41741 , H01L29/41766 , H01L29/452 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A manufacturing method of a semiconductor device includes the steps of: forming a first electrode layer on a n-type semiconductor layer; forming a second electrode layer on a p-type semiconductor layer; and performing heat treatment for the first electrode layer and the second electrode layer formed on the semiconductor layers. Temperature of the heat treatment is not lower than 400 degrees centigrade and not higher than 650 degrees centigrade.
摘要翻译：半导体器件的制造方法包括以下步骤：在n型半导体层上形成第一电极层; 在p型半导体层上形成第二电极层; 对形成在半导体层上的第一电极层和第二电极层进行热处理。热处理温度不低于400摄氏度，不高于650摄氏度。

10. 发明授权

US09508822B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09508822B2
公开(公告)日：2016-11-29
申请号：US14205128
申请日：2014-03-11
申请人： TOYODA GOSEI CO., LTD.
发明人： Toru Oka , Takahiro Sonoyama
IPC分类号： H01L21/02 , H01L29/51 , H01L29/778 , H01L29/20 , H01L29/78 , H01L29/423
CPC分类号： H01L29/513 , H01L29/2003 , H01L29/4236 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/66522 , H01L29/66666 , H01L29/7786 , H01L29/7813 , H01L29/7827 , H01L29/7835
摘要： A semiconductor device comprises: a gate insulating film 190 stacked on a semiconductor layer 130; and a gate electrode layer 230 stacked on the gate insulating film 190 and provided to apply a voltage via the gate insulating film 190 for formation of a channel in the semiconductor layer 130. The gate insulating film 190 includes: a first insulation film 192 stacked on the semiconductor layer 130; and a second insulation film 194 between the first insulation film 192 and the gate electrode layer 230. When ∈1 and ∈2 respectively represent relative permittivities of the first and second insulation film 192, 194, d1 [nm] and d2 [nm] represent film thicknesses of the first and second insulation film 192, 194, and Vmax [V] represents a rated voltage applicable to the gate electrode layer 230, the semiconductor device is configured to satisfy ∈1
摘要翻译：半导体器件包括：堆叠在半导体层130上的栅极绝缘膜190; 以及层叠在栅极绝缘膜190上并设置成经由栅极绝缘膜190施加电压以在半导体层130中形成沟道的栅电极层230.栅极绝缘膜190包括：堆叠在第一绝缘膜192上的第一绝缘膜192 半导体层130; 以及第一绝缘膜192和栅极电极层230之间的第二绝缘膜194.当第一和第二绝缘膜192分别表示第一绝缘膜192和第二绝缘膜194的相对介电常数，d1 [nm]和d2 [nm ]表示第一绝缘膜192和第二绝缘膜194的膜厚度，Vmax [V]表示可应用于栅极电极层230的额定电压，半导体器件被配置为满足＆lt; 1＆）：Vmaxɛɛɛɛɛɛ2 2;;;;;;;;; 21 [MV / cm]（C1）

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