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1. 发明申请

US20230061485A1 Method of Forming A Semiconductor Device 有权
公开(公告)号：US20230061485A1
公开(公告)日：2023-03-02
申请号：US17463000
申请日：2021-08-31
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chia-Cheng Chen , Chun-Hung Wu , Liang-Yin Chen , Huicheng Chang , Yee-Chia Yeo , Chun-Yen Chang , Chih-Kai Yang , Yu-Tien Shen , Ya Hui Chang
IPC分类号： H01L21/027 , H01L21/311 , H01L21/768
摘要： A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

2. 发明授权

US09026955B1 Methodology for pattern correction 有权
标题翻译：模式校正方法
公开(公告)号：US09026955B1
公开(公告)日：2015-05-05
申请号：US14051568
申请日：2013-10-11
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Hung-Chun Wang , Ming-Hui Chih , Ping-Chieh Wu , Chun-Hung Wu , Feng-Ju Chang , Cheng-Kun Tsai , Wen-Chun Huang , Ru-Gun Liu
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F7/70433 , H01L21/3212 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.
摘要翻译：本公开涉及通过分开校正IC设计的主要特征形状和虚拟形状以及相关联的装置来减少图案校正周期时间的集成芯片（IC）设计图案校正的方法。在一些实施例中，通过形成具有多个主要特征形状的IC设计来执行该方法。将多个虚拟形状添加到IC设计中以改善IC设计的处理窗口。使用第一图案校正处理来校正多个主要特征形状。随后使用与第一图案校正处理分开的第二图案校正处理来校正多个虚拟形状中的一个或多个。通过单独地校正虚拟形状和主要特征形状，可以对虚拟形状进行具有较低时间/资源需求的不同的图案校正处理，从而减少图案校正周期时间。

3. 发明申请

US20220406592A1 SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME 有权
公开(公告)号：US20220406592A1
公开(公告)日：2022-12-22
申请号：US17651851
申请日：2022-02-21
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chun-Hung Wu , Chia-Cheng Chen , Liang-Yin Chen , Huicheng Chang , Yee-Chia Yeo
IPC分类号： H01L21/027 , H01L21/311 , H01L21/3213
摘要： A method of forming a semiconductor device includes forming a photoresist over a target layer, where the target layer includes a substrate. The photoresist is patterned to form a patterned photoresist. Scum remains between portions of the patterned photoresist. The substrate is tilted relative to a direction of propagation of an ion beam. An ion treatment is performed on the scum. A pattern of the patterned photoresist is transferred to the target layer.

4. 发明申请

US20210226008A1 Doping for Semiconductor Device with Conductive Feature 有权
公开(公告)号：US20210226008A1
公开(公告)日：2021-07-22
申请号：US17201041
申请日：2021-03-15
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Su-Hao Liu , Huicheng Chang , Chia-Cheng Chen , Liang-Yin Chen , Kuo-Ju Chen , Chun-Hung Wu , Chang-Maio Liu , Huai-Tei Yang , Lun-Kuang Tan , Wei-Ming You
IPC分类号： H01L29/08 , H01L29/167 , H01L29/78 , H01L21/02 , H01L21/285 , H01L29/66 , H01L21/265 , H01L29/417
摘要： The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

5. 发明授权

US10950694B2 Doping for semiconductor device with conductive feature 有权
公开(公告)号：US10950694B2
公开(公告)日：2021-03-16
申请号：US16433374
申请日：2019-06-06
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Su-Hao Liu , Huicheng Chang , Chia-Cheng Chen , Liang-Yin Chen , Kuo-Ju Chen , Chun-Hung Wu , Chang-Maio Liu , Huai-Tei Yang , Lun-Kuang Tan , Wei-Ming You
IPC分类号： H01L29/78 , H01L29/08 , H01L29/167 , H01L21/02 , H01L21/285 , H01L29/66 , H01L21/265 , H01L29/417
摘要： The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

6. 发明授权

US09411924B2 Methodology for pattern density optimization 有权
标题翻译：模式密度优化方法
公开(公告)号：US09411924B2
公开(公告)日：2016-08-09
申请号：US14051549
申请日：2013-10-11
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Hung-Chun Wang , Ming-Hui Chih , Ping-Chieh Wu , Chun-Hung Wu , Wen-Hao Liu , Cheng-Hsuan Huang , Cheng-Kun Tsai , Wen-Chun Huang , Ru-Gun Liu
IPC分类号： G06F17/50 , G03F1/36
CPC分类号： G06F17/5081 , G03F1/36
摘要： The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced.
摘要翻译：本公开涉及一种利用低OPC（光学邻近校正）周期时间改进图案密度的方法，以及相关联的装置。在一些实施例中，该方法通过形成作为集成芯片的图形表示的集成芯片（IC）设计来执行。识别IC设计中的一个或多个低图案密度区域具有导致处理失败的图案密度。低图案密度区域是IC设计的一个子集。通过在低图案密度区域内添加一个或多个虚拟形状，在低图案密度区域内调整图案密度。然后对IC设计执行数据准备处理，以修改低图案密度区域内的一个或多个虚拟形状的形状。通过将虚拟形状引入局部区域而不是整个集成芯片设计中，随后的数据准备过程的需求减少。

7. 发明申请

US20220310785A1 Semiconductor Devices Including Backside Power Rails and Methods of Manufacture 有权
公开(公告)号：US20220310785A1
公开(公告)日：2022-09-29
申请号：US17566316
申请日：2021-12-30
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chun-Hung Wu , Chia-Ling Chung , Su-Hao Liu , Liang-Yin Chen , Shun-Wu Lin , Huicheng Chang , Yee-Chia Yeo
IPC分类号： H01L29/06 , H01L29/786 , H01L21/8234 , H01L21/425
摘要： A method of forming a semiconductor device including performing an ion implantation on a substrate and etching the substrate and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a transistor on a first side of a substrate; performing an ion implantation on a second side of the substrate opposite the first side; after performing the ion implantation, etching the substrate to remove the substrate and form a first recess; and forming a dielectric layer in the first recess.

8. 发明授权

US11450741B2 Doping for semiconductor device with conductive feature 有权
公开(公告)号：US11450741B2
公开(公告)日：2022-09-20
申请号：US17201041
申请日：2021-03-15
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Su-Hao Liu , Huicheng Chang , Chia-Cheng Chen , Liang-Yin Chen , Kuo-Ju Chen , Chun-Hung Wu , Chang-Miao Liu , Huai-Tei Yang , Lun-Kuang Tan , Wei-Ming You
IPC分类号： H01L21/8234 , H01L29/08 , H01L29/167 , H01L29/78 , H01L21/02 , H01L21/285 , H01L29/66 , H01L21/265 , H01L29/417
摘要： The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

9. 发明授权

US10049178B2 Methodology for pattern density optimization 有权
公开(公告)号：US10049178B2
公开(公告)日：2018-08-14
申请号：US15170026
申请日：2016-06-01
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Hung-Chun Wang , Ming-Hui Chih , Ping-Chieh Wu , Chun-Hung Wu , Wen-Hao Liu , Cheng-Hsuan Huang , Cheng-Kun Tsai , Wen-Chun Huang , Ru-Gun Liu
IPC分类号： G06F17/50 , G03F1/36
摘要： The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.

10. 发明申请

US20230042196A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE 有权
公开(公告)号：US20230042196A1
公开(公告)日：2023-02-09
申请号：US17670740
申请日：2022-02-14
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yu-Chang Lin , Chun-Hung Wu , Liang-Yin Chen , Huicheng Chang , Yee-Chia Yeo
IPC分类号： H01L29/06 , H01L29/786 , H01L21/8234
摘要： A method includes depositing a multi-layer stack over a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a first recess in the multi-layer stack; forming first spacers on sidewalls of the sacrificial layers in the first recess; depositing a first semiconductor material in the first recess, where the first semiconductor material is undoped, where the first semiconductor material is in physical contact with a sidewall and a bottom surface of at least one of the first spacers; implanting dopants in the first semiconductor material, where after implanting dopants the first semiconductor material has a gradient-doped profile; and forming an epitaxial source/drain region in the first recess over the first semiconductor material, where a material of the epitaxial source/drain region is different from the first semiconductor material.

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