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1. 发明申请

US20220262926A1 Fin Field-Effect Transistor Device and Method 有权
公开(公告)号：US20220262926A1
公开(公告)日：2022-08-18
申请号：US17728633
申请日：2022-04-25
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Che-Lun Chang , Shiao-Shin Cheng , Ji-Yin Tsai , Yu-Lin Tsai , Hsin-Chieh Huang , Ming-Yuan Wu , Jiun-Ming Kuo , Ming-Jie Huang , Yu-Wen Wang , Che-Yuan Hsu
IPC分类号： H01L29/66 , H01L21/02 , H01L29/78 , H01L29/165 , H01L29/08
摘要： A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.

2. 发明申请

US20190252323A1 INTEGRATED FAN-OUT PACKAGE 审中-公开
公开(公告)号：US20190252323A1
公开(公告)日：2019-08-15
申请号：US16396794
申请日：2019-04-29
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ming-Yen Chiu , Ching-Fu Chang , Hsin-Chieh Huang
IPC分类号： H01L23/538 , H01L23/31 , H01L49/02 , H01L21/683 , H01L23/66
摘要： An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.

3. 发明授权

US10326006B2 FinFET device and fabricating method thereof 有权
公开(公告)号：US10326006B2
公开(公告)日：2019-06-18
申请号：US16229026
申请日：2018-12-21
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yen-Ming Peng , Chi-Wen Liu , Hsin-Chieh Huang , Yi-Ju Hsu , Horng-Huei Tseng
IPC分类号： H01L21/70 , H01L29/66 , H01L29/78
摘要： A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.

4. 发明授权

US10276506B2 Integrated fan-out package 有权
公开(公告)号：US10276506B2
公开(公告)日：2019-04-30
申请号：US15215594
申请日：2016-07-21
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ming-Yen Chiu , Ching-Fu Chang , Hsin-Chieh Huang
IPC分类号： H01L23/538 , H01L49/02 , H01L23/66 , H01L23/31
摘要： A semiconductor device including an integrated circuit, a protection layer, and a conductive via is provided. The integrated circuit includes at least one conductive pad. The protection layer covers the integrated circuit. The protection layer includes a contact opening, and the conductive pad is exposed by the contact opening of the protection layer. The conductive via is embedded in the contact opening of the protection layer, and the conductive via is electrically connected to the conductive pad through the contact opening. A method of fabricating the above-mentioned semiconductor device and an integrated fan-out package including the above-mentioned semiconductor device are also provided.

5. 发明授权

US10037961B2 Integrated fan-out package and method of fabricating the same 有权
公开(公告)号：US10037961B2
公开(公告)日：2018-07-31
申请号：US15156339
申请日：2016-05-17
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ming-Yen Chiu , Ching-Fu Chang , Hsin-Chieh Huang
IPC分类号： H01L23/00 , H01L23/48 , H01L23/544 , H01L23/31 , H01L21/768 , H01L21/56 , H01L21/3105 , H01L21/683 , H01L25/065 , H01L21/78
CPC分类号： H01L24/14 , H01L21/31053 , H01L21/568 , H01L21/6835 , H01L21/76885 , H01L21/78 , H01L23/3107 , H01L23/3192 , H01L23/481 , H01L23/49811 , H01L23/5389 , H01L23/544 , H01L24/06 , H01L24/20 , H01L25/0657 , H01L2221/68327 , H01L2221/68359 , H01L2224/0231 , H01L2224/0237 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/13014 , H01L2224/13016 , H01L2224/13023 , H01L2224/13024 , H01L2224/13025 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/16238 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06548 , H01L2924/05042 , H01L2924/05442 , H01L2924/059 , H01L2924/06 , H01L2924/07025 , H01L2924/14 , H01L2224/03 , H01L2924/014
摘要： An integrated fan-out package including an integrated circuit, an insulating encapsulation, a plurality of conductive through vias, and a redistribution circuit structure is provided. The integrated circuit includes a plurality of conductive terminals. The insulating encapsulation encapsulates sidewalls of the integrated circuit. The conductive through vias penetrate in the insulating encapsulation. The redistribution circuit structure is disposed on the integrated circuit, the conductive through vias and the insulating encapsulation. The redistribution conductive layer is electrically connected to the conductive terminals and the conductive through vias. A plurality of first contact surfaces of the conductive terminals and a plurality of second contact surfaces of the conductive through vias are in contact with the redistribution circuit structure, and a roughness of the first contact surfaces and the second contact surfaces ranges from 100 angstroms to 500 angstroms. Methods of fabricating the integrated fan-out package are also provided.

6. 发明授权

US09941216B2 Conductive pattern and integrated fan-out package having the same 有权
公开(公告)号：US09941216B2
公开(公告)日：2018-04-10
申请号：US15281043
申请日：2016-09-29
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ming-Yen Chiu , Ching-Fu Chang , Chien-Chia Chiu , Hsin-Chieh Huang , Tsung-Shu Lin , Pei-Ti Yu
IPC分类号： H01L23/538 , H01L25/10
CPC分类号： H01L23/5386 , H01L21/4857 , H01L21/486 , H01L21/568 , H01L23/49811 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311
摘要： A conductive pattern including a teardrop shaped portion, a routing line, and a connection portion is provided. The routing line links to the teardrop shaped portion through the connection portion, and a width of the connection portion decreases along an extending direction from the teardrop shaped portion to the routing line. Furthermore, an integrated fan-out package including the above-mentioned conductive pattern is also provided.

7. 发明申请

US20170294391A1 DICING TECHNIQUES FOR POWER TRANSISTORS 审中-公开
公开(公告)号：US20170294391A1
公开(公告)日：2017-10-12
申请号：US15631392
申请日：2017-06-23
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yu-Syuan Lin , Jiun-Lei Jerry Yu , Ming-Cheng Lin , Hsin-Chieh Huang , Chao-Hsiung Wang
IPC分类号： H01L23/58 , H01L29/778 , H01L29/40 , H01L21/78 , H01L29/20
CPC分类号： H01L23/585 , H01L21/78 , H01L21/784 , H01L23/5226 , H01L23/562 , H01L29/0657 , H01L29/2003 , H01L29/402 , H01L29/7786 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments relate to a die that has been formed by improved dicing techniques. The die includes a substrate which includes upper and lower substrate surfaces with a vertical substrate sidewall extending therebetween. The vertical substrate sidewall corresponds to an outermost edge of the substrate. A device layer is arranged over the upper substrate surface. A crack stop is arranged over an upper surface of the device layer and has an outer perimeter that is spaced apart laterally from the vertical substrate sidewall. The die exhibits a tapered sidewall extending downward through at least a portion of the device layer to meet the vertical substrate sidewall.

8. 发明申请

US20170069757A1 FINFET DEVICE AND FABRICATING METHOD THEREOF 审中-公开
标题翻译： FINFET器件及其制造方法
公开(公告)号：US20170069757A1
公开(公告)日：2017-03-09
申请号：US14994057
申请日：2016-01-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Yen-Ming Peng , Chi-Wen Liu , Hsin-Chieh Huang , Yi-Ju Hsu , Horng-Huei Tseng
IPC分类号： H01L29/78 , H01L29/66 , H01L29/49 , H01L29/423
CPC分类号： H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
摘要翻译： FinFET器件包括衬底，形成在衬底上的鳍片和与鳍片交叉的栅极电极。栅电极包括头部和尾部，尾部连接到头部并朝向衬底延伸。头部的宽度大于尾部的宽度。

9. 发明申请

US20170016851A1 INTEGRATED BIOSENSOR 有权
标题翻译：集成生物传感器
公开(公告)号：US20170016851A1
公开(公告)日：2017-01-19
申请号：US15277108
申请日：2016-09-27
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chun-Wen Cheng , Fei-Lung Lai , Chia-Hua Chu , Yi-Hsien Chang , Hsin-Chieh Huang
IPC分类号： G01N27/414 , H01L23/522 , H01L23/528 , H01L21/48
CPC分类号： G01N27/4148 , G01N27/4145 , H01L21/486 , H01L23/5226 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to an integrated chip having an integrated bio-sensor with horizontal and vertical sensing surfaces. In some embodiments, the integrated chip has a sensing device disposed within a substrate, and a lower metal wire over the substrate and electrically coupled to the sensing device. First and second metal vias are arranged on the lower metal wire at locations set back from sidewalls of the lower metal wire, and first and second upper metal wires respectively cover top surfaces of the first and second metal vias. A dielectric structure surrounds the lower metal wire, the first and second metal vias, and the first and second upper metal wires. A sensing well has sensing surfaces that extend along an upper surface of the lower metal wire and along sidewalls of the first and second metal vias and the first and second upper metal wires.
摘要翻译：本公开涉及具有具有水平和垂直感测表面的集成生物传感器的集成芯片。在一些实施例中，集成芯片具有设置在衬底内的感测装置，以及位于衬底上的电子耦合到感测装置的下部金属线。第一和第二金属通孔设置在下金属线上，从下金属线的侧壁设置的位置，第一和第二上金属线分别覆盖第一和第二金属通孔的顶表面。电介质结构围绕下金属线，第一和第二金属通孔以及第一和第二上金属线。感测井具有沿着下金属线的上表面并且沿着第一和第二金属通孔以及第一和第二上金属线的侧壁延伸的感测表面。

10. 发明申请

US20160204074A1 DICING METHOD FOR POWER TRANSISTORS 有权
标题翻译：功率晶体管的定义方法
公开(公告)号：US20160204074A1
公开(公告)日：2016-07-14
申请号：US14596326
申请日：2015-01-14
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yu-Syuan Lin , Jiun-Lei Jerry Yu , Ming-Cheng Lin , Hsin-Chieh Huang , Chao-Hsiung Wang
IPC分类号： H01L23/00 , H01L23/522 , H01L23/58 , H01L29/20 , H01L29/78
CPC分类号： H01L23/585 , H01L21/78 , H01L21/784 , H01L23/5226 , H01L23/562 , H01L29/0657 , H01L29/2003 , H01L29/402 , H01L29/7786 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments relate to a method of dicing a semiconductor wafer. The semiconductor wafer that includes a device structure that is formed within a device layer. The device layer is arranged within an upper surface the device layer. A crack stop is formed, which surrounds the device structure and reinforces the semiconductor wafer to prevent cracking during dicing. A laser is used to form a groove along a scribe line outside the crack stop. The groove extends completely through the device layer, and into an upper surface region of the semiconductor wafer. The semiconductor wafer is then cut along the grooved scribe line with a cutting blade to singulate the semiconductor wafer into two or more die. By extending the groove completely through the device layer, the method avoids damage to the device layer caused by the blade saw, and thus avoids an associated performance degradation of the device structure.
摘要翻译：一些实施例涉及切割半导体晶片的方法。该半导体晶片包括在器件层内形成的器件结构。器件层布置在器件层的上表面内。形成裂缝停止件，其围绕装置结构并加强半导体晶片以防止切割期间的开裂。使用激光器沿着裂纹停止点外的划线形成凹槽。凹槽完全延伸穿过器件层并进入半导体晶片的上表面区域。然后用切割刀沿着带槽划线切割半导体晶片，将半导体晶片分成两个或更多个管芯。通过将槽完全延伸穿过器件层，该方法避免了由刀片锯引起的对器件层的损坏，从而避免了器件结构的相关性能下降。

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