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    • 4. 发明授权
    • CMOS cascode power cells
    • CMOS共源共栅电源
    • US09071203B2
    • 2015-06-30
    • US13939209
    • 2013-07-11
    • Taiwan Semiconductor Manufacturing Co., Ltd.
    • Tzu-Jin YehChewn-Pu JouJun-De JinHsieh-Hung HsiehChia-Chung Chen
    • H03F3/14H03F3/213H01L21/8238H03F1/22
    • H03F3/213H01L21/8238H01L27/092H01L2924/3011H03F1/223
    • A circuit includes a first CMOS device forming a gain stage of a power amplifier and a second CMOS device forming a voltage buffer stage of the power amplifier. The first CMOS device includes a first doped well formed in a substrate, a first drain region and a first source region spaced laterally from one another in the first doped well, and a first gate structure formed over a first channel region in the first doped well. The second CMOS device includes a second doped well formed in the semiconductor substrate such that the first doped well and the second is disposed adjacent to the second doped well. A second drain region and a second source region are spaced laterally from one another in the second doped well, and a second gate structure formed over a second channel region in the second doped well.
    • 电路包括形成功率放大器的增益级的第一CMOS器件和形成功率放大器的电压缓冲级的第二CMOS器件。 第一CMOS器件包括形成在衬底中的第一掺杂阱,第一漏极区和在第一掺杂阱中彼此横向间隔开的第一源极区,以及形成在第一掺杂阱中的第一沟道区上的第一栅极结构 。 第二CMOS器件包括在半导体衬底中形成的第二掺杂阱,使得第一掺杂阱和第二掺杂阱邻近第二掺杂阱设置。 第二漏极区域和第二源极区域在第二掺杂阱中彼此横向隔开,第二栅极结构形成在第二掺杂阱中的第二沟道区域上。