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1. 发明授权

US10325849B2 Different scaling ratio in FEOL/ MOL/ BEOL 有权
公开(公告)号：US10325849B2
公开(公告)日：2019-06-18
申请号：US15016448
申请日：2016-02-05
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Liang-Yao Lee , Tsung-Chieh Tsai , Juing-Yi Wu , Chun-Yi Lee
IPC分类号： G06F17/50 , H01L23/528 , H01L23/522 , H01L29/49
摘要： In some embodiments, the present disclosure relates to an integrated chip. The integrated chip has a plurality of gate structures arranged over a substrate. A plurality of first MOL (middle-of-line) structures are arranged at a first pitch over the substrate at locations interleaved between the plurality of gate structures. The plurality of first MOL structures connect active regions within the substrate to an overlying metal interconnect layer. A plurality of second MOL structures are arranged at a second pitch over the plurality of gate structures at locations interleaved between the plurality of first MOL structures. The plurality of second MOL structures connect the plurality of gate structures to the metal interconnect layer. The second pitch is different than the first pitch. The different pitches avoid misalignment errors between the plurality of gate structures and the metal interconnect layer.

2. 发明授权

US09292649B2 Different scaling ratio in FEOL / MOL/ BEOL 有权
标题翻译： FEOL / MOL / BEOL中的不同缩放比例
公开(公告)号：US09292649B2
公开(公告)日：2016-03-22
申请号：US14082487
申请日：2013-11-18
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Liang-Yao Lee , Tsung-Chieh Tsai , Juing-Yi Wu , Chun-Yi Lee
IPC分类号： G06F17/50
CPC分类号： H01L23/5283 , G06F17/5068 , G06F17/5081 , H01L23/5226 , H01L29/4916 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to a method of generating a scaled integrated chip design by scaling a FEOL and a BEOL of an original IC design at different scaling ratios, and an associated apparatus. In some embodiments, the method is performed by forming an original integrated chip (IC) design that is a graphical representation of an integrated chip. The original IC design has a front-end-of-the-line (FEOL) section, a back-end-of-the-line (BEOL) section, and a middle-of-the-line (MOL) section that is disposed between the FEOL and BEOL sections. A scaled integrated chip design is formed by scaling (i.e., shrinking) the FEOL section and the BEOL section of the original integrated chip design at different scaling ratios, and by scaling different design layers within the MOL section at different scaling ratios to avoid misalignment errors between the FEOL section and the BEOL section.
摘要翻译：本公开涉及通过以不同的缩放比率缩放原始IC设计的FEOL和BEOL以及相关联的装置来生成缩放的集成芯片设计的方法。在一些实施例中，该方法通过形成作为集成芯片的图形表示的原始集成芯片（IC）设计来执行。原始IC设计具有前端（FEOL）部分，后端（BEOL）部分和中间线（MOL）部分设置在FEOL和BEOL部分之间。通过缩放（即收缩）原始集成芯片设计的FEOL部分和BEOL部分以不同的缩放比例，并以不同的缩放比例缩放MOL部分内的不同设计层来形成缩放的集成芯片设计，以避免错位错误在FEOL部分和BEOL部分之间。

3. 发明申请

US20150143319A1 DIFFERENT SCALING RATIO IN FEOL / MOL/ BEOL 有权
标题翻译： FEOL / MOL / BEOL中的不同缩放比例
公开(公告)号：US20150143319A1
公开(公告)日：2015-05-21
申请号：US14082487
申请日：2013-11-18
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Liang-Yao Lee , Tsung-Chieh Tsai , Juing-Yi Wu , Chun-Yi Lee
IPC分类号： G06F17/50
CPC分类号： H01L23/5283 , G06F17/5068 , G06F17/5081 , H01L23/5226 , H01L29/4916 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to a method of generating a scaled integrated chip design by scaling a FEOL and a BEOL of an original IC design at different scaling ratios, and an associated apparatus. In some embodiments, the method is performed by forming an original integrated chip (IC) design that is a graphical representation of an integrated chip. The original IC design has a front-end-of-the-line (FEOL) section, a back-end-of-the-line (BEOL) section, and a middle-of-the-line (MOL) section that is disposed between the FEOL and BEOL sections. A scaled integrated chip design is formed by scaling (i.e., shrinking) the FEOL section and the BEOL section of the original integrated chip design at different scaling ratios, and by scaling different design layers within the MOL section at different scaling ratios to avoid misalignment errors between the FEOL section and the BEOL section.
摘要翻译：本公开涉及通过以不同的缩放比率缩放原始IC设计的FEOL和BEOL以及相关联的装置来生成缩放的集成芯片设计的方法。在一些实施例中，该方法通过形成作为集成芯片的图形表示的原始集成芯片（IC）设计来执行。原始IC设计具有前端（FEOL）部分，后端（BEOL）部分和中间线（MOL）部分设置在FEOL和BEOL部分之间。通过缩放（即收缩）原始集成芯片设计的FEOL部分和BEOL部分以不同的缩放比例，并以不同的缩放比例缩放MOL部分内的不同设计层来形成缩放的集成芯片设计，以避免错位错误在FEOL部分和BEOL部分之间。

4. 发明授权

US11152303B2 Different scaling ratio in FEOL / MOL/ BEOL 有权
公开(公告)号：US11152303B2
公开(公告)日：2021-10-19
申请号：US16432078
申请日：2019-06-05
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Liang-Yao Lee , Tsung-Chieh Tsai , Juing-Yi Wu , Chun-Yi Lee
IPC分类号： H01L23/522 , H01L29/49 , H01L27/02 , G06F30/39 , H01L29/06 , H01L23/528 , G06F30/398
摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a plurality of gate structures disposed over a substrate. A plurality of metal structures continuously extend from lower surfaces contacting the plurality of gate structures to upper surfaces contacting one or more interconnects within an overlying conductive interconnect layer. The plurality of metal structures are arranged at a first pitch that is larger than a second pitch of the plurality of gate structures.

5. 发明申请

US20150050810A1 METHOD FOR PREVENTING PHOTORESIST CORNER ROUNDING EFFECTS 有权
标题翻译：防止光电角环绕效应的方法
公开(公告)号：US20150050810A1
公开(公告)日：2015-02-19
申请号：US13967477
申请日：2013-08-15
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Liang-Yao Lee , Jyh-Kang Ting , Tsung-Chieh Tsai , Juing-Yu Wu
IPC分类号： H01L21/308
CPC分类号： G03F7/70441 , G03F1/36 , G03F7/70283
摘要： A method for ameliorating corner rounding effects in a photolithographic process is provided. A semiconductor workpiece having an active device region is provided, and a photoresist layer is formed over the semiconductor workpiece. A mask is provided for patterning for the photoresist layer, wherein the mask comprises pattern having a sharp corner associated with the active device region. The sharp corner is separated from the active device region by a first distance in a first direction and a second distance in a second direction, wherein the first distance meets a minimum criteria for the photolithographic process, and wherein the second distance is greater than the first distance. The photoresist layer is then exposed to a radiation source, and the radiation source patterns the photoresist layer through the mask, defining an exposure region on the semiconductor workpiece having a rounded corner associated with the sharp corner. Accordingly, the second distance generally prevents the rounded corner of the exposure region from overlapping the active device region.
摘要翻译：提供了一种用于在光刻工艺中改善拐角圆角效果的方法。提供具有有源器件区域的半导体工件，并且在半导体工件上形成光致抗蚀剂层。提供掩模用于图案化光致抗蚀剂层，其中掩模包括具有与有源器件区域相关联的尖角的图案。尖角与有源器件区分离第一方向第一距离和第二方向上的第二距离，其中第一距离满足光刻工艺的最小标准，并且其中第二距离大于第一距离距离。然后将光致抗蚀剂层暴露于辐射源，并且辐射源通过掩模对光致抗蚀剂层进行图案，在半导体工件上限定具有与锐角相关的圆角的曝光区域。因此，第二距离通常防止曝光区域的圆角与有源器件区域重叠。

6. 发明授权

US09746783B2 Method for preventing photoresist corner rounding effects 有权
公开(公告)号：US09746783B2
公开(公告)日：2017-08-29
申请号：US13967477
申请日：2013-08-15
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Liang-Yao Lee , Jyh-Kang Ting , Tsung-Chieh Tsai , Juing-Yi Wu
IPC分类号： H01L21/308 , G03F7/20 , G03F1/36
CPC分类号： G03F7/70441 , G03F1/36 , G03F7/70283
摘要： A method for ameliorating corner rounding effects in a photolithographic process is provided. A semiconductor workpiece having an active device region is provided, and a photoresist layer is formed over the semiconductor workpiece. A mask is provided for patterning for the photoresist layer, wherein the mask comprises pattern having a sharp corner associated with the active device region. The sharp corner is separated from the active device region by a first distance in a first direction and a second distance in a second direction, wherein the first distance meets a minimum criteria for the photolithographic process, and wherein the second distance is greater than the first distance. The photoresist layer is then exposed to a radiation source, and the radiation source patterns the photoresist layer through the mask, defining an exposure region on the semiconductor workpiece having a rounded corner associated with the sharp corner. Accordingly, the second distance generally prevents the rounded corner of the exposure region from overlapping the active device region.

7. 发明申请

US20190287905A1 DIFFERENT SCALING RATIO IN FEOL / MOL/ BEOL 审中-公开
公开(公告)号：US20190287905A1
公开(公告)日：2019-09-19
申请号：US16432078
申请日：2019-06-05
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Liang-Yao Lee , Tsung-Chieh Tsai , Juing-Yi Wu , Chun-Yi Lee
IPC分类号： H01L23/528 , H01L29/49 , H01L23/522 , G06F17/50
摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a plurality of gate structures disposed over a substrate. A plurality of metal structures continuously extend from lower surfaces contacting the plurality of gate structures to upper surfaces contacting one or more interconnects within an overlying conductive interconnect layer. The plurality of metal structures are arranged at a first pitch that is larger than a second pitch of the plurality of gate structures.

8. 发明授权

US10366900B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US10366900B2
公开(公告)日：2019-07-30
申请号：US15081800
申请日：2016-03-25
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Juing-Yi Wu , Liang-Yao Lee , Tsung-Chieh Tsai
IPC分类号： H01L21/3105 , H01L21/265 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L21/768
摘要： In a method for manufacturing a semiconductor device, a first dielectric layer is formed over an underlying structure disposed on a substrate. A planarization resistance layer is formed over the first dielectric layer. A second dielectric layer is formed over the first dielectric layer and the planarization resistance layer. A planarization operation is performed on the second dielectric layer, the planarization resistance layer and the first dielectric layer. The planarization resistance film is made of a material different from the first dielectric layer.

9. 发明申请

US20160155704A1 DIFFERENT SCALING RATIO IN FEOL / MOL/ BEOL 审中-公开
标题翻译： FEOL / MOL / BEOL中的不同缩放比例
公开(公告)号：US20160155704A1
公开(公告)日：2016-06-02
申请号：US15016448
申请日：2016-02-05
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Liang-Yao Lee , Tsung-Chieh Tsai , Juing-Yi Wu , Chun-Yi Lee
IPC分类号： H01L23/528 , H01L29/49 , H01L23/522
CPC分类号： H01L23/5283 , G06F17/5068 , G06F17/5081 , H01L23/5226 , H01L29/4916 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments, the present disclosure relates to an integrated chip. The integrated chip has a plurality of gate structures arranged over a substrate. A plurality of first MOL (middle-of-line) structures are arranged at a first pitch over the substrate at locations interleaved between the plurality of gate structures. The plurality of first MOL structures connect active regions within the substrate to an overlying metal interconnect layer. A plurality of second MOL structures are arranged at a second pitch over the plurality of gate structures at locations interleaved between the plurality of first MOL structures. The plurality of second MOL structures connect the plurality of gate structures to the metal interconnect layer. The second pitch is different than the first pitch. The different pitches avoid misalignment errors between the plurality of gate structures and the metal interconnect layer.
摘要翻译：在一些实施例中，本公开涉及集成芯片。集成芯片具有布置在衬底上的多个栅极结构。多个第一MOL（中线）结构在交错在多个栅极结构之间的位置处以衬底上的第一间距布置。多个第一MOL结构将衬底内的有源区连接到上覆金属互连层。在多个第一MOL结构之间交错的位置处，多个第二MOL结构以多个门结构以第二间距布置。多个第二MOL结构将多个栅极结构连接到金属互连层。第二音调与第一音高不同。不同的间距避免了多个栅极结构和金属互连层之间的错位。

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