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1. 发明授权

US12051732B2 Semiconductor structure and method for forming the same 有权
公开(公告)号：US12051732B2
公开(公告)日：2024-07-30
申请号：US17400446
申请日：2021-08-12
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuan-Hao Cheng , Wei-Yang Lee , Tzu-Hua Chiu , Wei-Han Fan , Po-Yu Lin , Chia-Pin Lin
IPC分类号： H01L29/423 , H01L29/06 , H01L29/66 , H01L29/786
CPC分类号： H01L29/42392 , H01L29/0673 , H01L29/66545 , H01L29/66636 , H01L29/66787 , H01L29/78618 , H01L29/78696
摘要： A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, and a first inner spacer layer interposing the gate stack and the source/drain feature and interposing the first nanostructure and the second nanostructure. A dopant in the source/drain feature has a first concentration at an interface between the first inner spacer layer and the source/drain feature and a second concentration at a first distance away from the interface. The first concentration is higher than the second concentration.

2. 发明授权

US12015090B2 Lightly-doped channel extensions 有权
公开(公告)号：US12015090B2
公开(公告)日：2024-06-18
申请号：US17813975
申请日：2022-07-21
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Wei-Jen Lai , Wei-Yuan Lu , Chih-Hao Yu , Chia-Pin Lin
IPC分类号： H01L29/786 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/08 , H01L29/165
CPC分类号： H01L29/78696 , H01L29/0653 , H01L29/42392 , H01L29/66545 , H01L29/66553 , H01L29/66742 , H01L29/66787 , H01L29/7848 , H01L29/78621 , H01L29/0847 , H01L29/165 , H01L29/78684
摘要： A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.

3. 发明授权

US12015060B2 Structure and formation method of semiconductor device with backside contact 有权
公开(公告)号：US12015060B2
公开(公告)日：2024-06-18
申请号：US17357052
申请日：2021-06-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Feng-Ching Chu , Wei-Yang Lee , Chia-Pin Lin
IPC分类号： H01L29/417 , H01L21/84 , H01L27/12 , H01L29/66 , H01L29/423 , H01L29/45 , H01L29/786
CPC分类号： H01L29/41733 , H01L21/84 , H01L27/12 , H01L29/66742 , H01L29/42392 , H01L29/458 , H01L29/78696
摘要： A semiconductor device structure and a formation method are provided. The semiconductor device structure includes a stack of channel structures and includes a first epitaxial structure and a second epitaxial structure adjacent to opposite sides of the channel structures. The semiconductor device structure also includes a gate stack wrapped around each of the channel structures and a backside conductive contact connected to the second epitaxial structure. The second epitaxial structure is between a top of the backside conductive contact and a top of the gate stack. The semiconductor device structure further includes a dielectric fin stacked over an isolation structure. The dielectric fin is adjacent to the second epitaxial structure, and the isolation structure is adjacent to the backside conductive contact. The isolation structure has a first height, the dielectric fin has a second height, and the second height is greater than the first height.

4. 发明公开

US20230395434A1 SEMICONDUCTOR DEVICE WITH LEAKAGE CURRENT SUPPRESSION AND METHOD FOR FORMING THE SAME 审中-公开
公开(公告)号：US20230395434A1
公开(公告)日：2023-12-07
申请号：US18447459
申请日：2023-08-10
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Bo-Yu Lai , Jyun-Chih Lin , Yen-Ting Chen , Wei-Yang Lee , Chia-Pin Lin , Wei Hao Lu , Li-Li Su
IPC分类号： H01L21/8238 , H01L29/423 , H01L21/764 , H01L29/66 , H01L29/786
CPC分类号： H01L21/823814 , H01L29/42392 , H01L29/78696 , H01L29/66545 , H01L29/6653 , H01L21/764
摘要： A semiconductor device includes a fin-shape base protruding from a substrate, channel structures suspended above the fin-shape base, a gate structure wrapping around each of the channel structures, a source/drain (S/D) epitaxial feature abutting the channel structures and directly above a top surface of the fin-shape base, inner spacers interposing the S/D epitaxial feature and the gate structure, and a dielectric layer disposed vertically between the top surface of the fin-shape base and a bottom surface of the S/D epitaxial feature.

5. 发明公开

US20230163186A1 EPITAXIAL FEATURES IN SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD OF THE SAME 审中-公开
公开(公告)号：US20230163186A1
公开(公告)日：2023-05-25
申请号：US17832609
申请日：2022-06-04
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chung-Chi Wen , Yen-Ting Chen , Wei-Yang Lee , Chih-Chiang Chang , Chien-I Kuo , Chia-Pin Lin
IPC分类号： H01L29/423 , H01L29/786 , H01L29/417 , H01L29/06 , H01L29/66
CPC分类号： H01L29/42392 , H01L29/78696 , H01L29/41775 , H01L29/0673 , H01L29/66545 , H01L29/66553
摘要： A method includes forming a semiconductor fin protruding from a substrate, forming a dummy gate structure across the semiconductor fin, recessing a portion of the semiconductor fin in a region adjacent the dummy gate structure to form a recess, growing a semiconductor layer in the recess, and forming a first dielectric layer interposing the semiconductor layer and the dummy gate structure. The semiconductor layer covers at least a portion of the first dielectric layer. The method also includes modifying a shape of the semiconductor layer to expose the portion of the first dielectric layer, depositing a second dielectric layer covering the semiconductor layer and the portion of the first dielectric layer, and replacing the dummy gate structure with a metal gate structure.

6. 发明申请

US20220359676A1 Asymmetric Source/Drain for Backside Source Contact 有权
公开(公告)号：US20220359676A1
公开(公告)日：2022-11-10
申请号：US17308678
申请日：2021-05-05
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Feng-Ching Chu , Wei-Yang Lee , Chia-Pin Lin
IPC分类号： H01L29/417 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/02 , H01L29/66
摘要： According to one example, a method includes performing a first etching process on a fin stack to form a first recess and a second recess at a first depth, the first recess and the second recess on opposite sides of a gate structure that is on the fin stack. The method further includes depositing inner spacers within the first recess and the second recess. The method further includes, after depositing the inner spacers, performing a second etching process to extend a depth of the first recess to a second depth. The method further includes forming a dummy contact region within the first recess, forming a source structure within the first recess on the dummy contact region, and forming a drain structure within the second recess.

7. 发明授权

US11328960B2 Semiconductor structure with gate-all-around devices and stacked FinFET devices 有权
公开(公告)号：US11328960B2
公开(公告)日：2022-05-10
申请号：US17027240
申请日：2020-09-21
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Feng-Ching Chu , Wei-Yang Lee , Chia-Pin Lin
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/423 , H01L29/786 , H01L29/66 , H01L21/02
摘要： An integrated circuit includes a stacked FinFET in a second area and a GAA transistor in a first area. The stacked FinFET includes two first source/drain, first and second semiconductor layers alternately stacked one over another and between the two first source/drain, a first gate dielectric layer over top and sidewalls of the first and second semiconductor layers, a first gate electrode layer over the first gate dielectric layer, and first spacer features laterally between the second semiconductor layers and the two first source/drain. The first and the second semiconductor layers include different materials. The GAA transistor includes two second source/drain, third semiconductor layers electrically connecting the two second source/drain, a second gate dielectric layer wrapping around the third semiconductor layers, a second gate electrode over the second gate dielectric layer, and second spacer features laterally between the second gate dielectric layer and the two second source/drain.

8. 发明申请

US20150111361A1 Integrated Circuit Resistor 有权
标题翻译：集成电路电阻
公开(公告)号：US20150111361A1
公开(公告)日：2015-04-23
申请号：US14586013
申请日：2014-12-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： King-Yuen Wong , Chia-Pin Lin , Chia-Yu Lu , Yi-Cheng Tsai , Da-Wen Lin , Kuo-Feng Yu
IPC分类号： H01L49/02 , H01L21/265 , H01L21/8234 , H01L21/02
CPC分类号： H01L28/20 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/26506 , H01L21/26513 , H01L21/823437 , H01L27/0629 , H01L29/66545 , H01L29/8605
摘要： A method of fabricating a semiconductor device is disclosed. The method includes providing a substrate including an isolation region, forming a resistor over the isolation region, and forming a contact over the resistor. The method also includes implanting with a dopant concentration that is step-increased at a depth of the resistor and that remains substantially constant as depth increases.
摘要翻译：公开了制造半导体器件的方法。该方法包括提供包括隔离区域的衬底，在隔离区域上形成电阻器，以及在电阻器上形成接触。该方法还包括以在电阻器的深度处逐步增加的掺杂剂浓度进行注入，并且随着深度增加而保持基本恒定。

9. 发明授权

US08575727B2 Gate structures 有权
标题翻译：门结构
公开(公告)号：US08575727B2
公开(公告)日：2013-11-05
申请号：US13886123
申请日：2013-05-02
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Peng-Soon Lim , Chia-Pin Lin , Kuang-Yuan Hsu
IPC分类号： H01L29/06
CPC分类号： H01L27/092 , H01L27/088 , H01L29/517 , H01L29/66545 , H01L29/66795 , H01L29/78 , H01L29/785
摘要： A semiconductor device is provided. The device includes a semiconductor substrate, first and second projections extending upwardly from the substrate, the projections having respective first and second channel regions therein, and a first gate structure engaging the first projection adjacent the first channel region. The first gate structure includes a first dielectric material over the first channel region, a first opening over the first dielectric material and the first channel region, and a pure first metal with an n-type work function value conformally deposited in the first opening. The device also includes a second gate structure engaging the second projection adjacent the second channel region. The second gate structure includes a second dielectric material over the second channel region, a second opening over the second dielectric material and the second channel region, and a pure second metal with a p-type work function value conformally deposited in the second opening.
摘要翻译：提供半导体器件。所述装置包括半导体衬底，从衬底向上延伸的第一和第二突起，所述突起在其中具有相应的第一和第二沟道区域，以及与第一沟道区域相邻的第一栅极结构。第一栅极结构包括在第一沟道区上方的第一介电材料，第一介电材料和第一沟道区上的第一开口，以及保形地沉积在第一开口中的具有n型功函数值的纯金属。该装置还包括与邻近第二通道区域的第二突起接合的第二栅极结构。第二栅极结构包括在第二沟道区上方的第二电介质材料，第二电介质材料和第二沟道区上的第二开口，以及保形地沉积在第二开口中的具有p型功函数值的纯的第二金属。

10. 发明授权

US12027626B2 Semiconductor device active region profile and method of forming the same 有权
公开(公告)号：US12027626B2
公开(公告)日：2024-07-02
申请号：US18066188
申请日：2022-12-14
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Feng-Ching Chu , Wei-Yang Lee , Chia-Pin Lin
IPC分类号： H01L29/78 , H01L21/3065 , H01L21/3213 , H01L21/762 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L29/7856 , H01L21/3065 , H01L21/32134 , H01L21/76224 , H01L29/0673 , H01L29/1037 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66818 , H01L29/775 , H01L29/78618 , H01L29/78696
摘要： Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

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