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1. 发明授权

US11574927B2 Semiconductor devices and method for manufacturing the same 有权
公开(公告)号：US11574927B2
公开(公告)日：2023-02-07
申请号：US17233162
申请日：2021-04-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Marcus Johannes Henricus Van Dal , Georgios Vellianitis , Gerben Doornbos
IPC分类号： H01L29/78 , H01L29/40 , H01L27/1159 , H01L21/28 , H01L29/24 , H01L29/51 , H01L29/16
摘要： A semiconductor device includes a gate electrode, a channel layer, and a ferroelectric layer. The ferroelectric layer includes a monocrystalline region located between the gate electrode and the channel layer to serve as a gate dielectric, and a polycrystalline region located at an edge of the gate electrode. A method for manufacturing the semiconductor device is also disclosed.

2. 发明申请

US20220384584A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20220384584A1
公开(公告)日：2022-12-01
申请号：US17878016
申请日：2022-07-31
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Georgios Vellianitis , Gerben Doornbos , Marcus Johannes Henricus Van Dal
IPC分类号： H01L29/22 , H01L29/78
摘要： A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a semiconductor layer and a gate structure located on the semiconductor layer. The semiconductor device has source and drain terminals disposed on the semiconductor layer, and a binary oxide layer located between the semiconductor layer and the source and drain terminals.

3. 发明授权

US09871104B2 Nanowire semiconductor device structure and method of manufacturing 有权
公开(公告)号：US09871104B2
公开(公告)日：2018-01-16
申请号：US14755083
申请日：2015-06-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Gerben Doornbos , Mark van Dal
IPC分类号： H01L21/265 , H01L29/66 , H01L29/04 , H01L29/08 , H01L29/78 , H01L29/06 , H01L21/324
CPC分类号： H01L29/0847 , H01L21/26506 , H01L21/26586 , H01L21/324 , H01L29/04 , H01L29/0673 , H01L29/0676 , H01L29/0688 , H01L29/167 , H01L29/42392 , H01L29/66439 , H01L29/66477 , H01L29/66666 , H01L29/775 , H01L29/78 , H01L29/7827
摘要： A nanowire comprises a source region, a drain region and a channel region. The source region is modified to reduce the lifetime of minority carriers within the source region. In an embodiment the modification may be performed by implanting either amorphizing dopants or lifetime reducing dopants. Alternatively, the source may be epitaxially grown with a different materials or process conditions to reduce the lifetime of minority carriers within the source region.

4. 发明申请

US20170365668A1 Semiconductor Device Channel System and Method 审中-公开
公开(公告)号：US20170365668A1
公开(公告)日：2017-12-21
申请号：US15676285
申请日：2017-08-14
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Gerben Doornbos , Krishna Kumar Bhuwalka , Matthias Passlack
IPC分类号： H01L29/205 , H01L29/10 , H01L29/66 , H01L29/78
CPC分类号： H01L29/205 , H01L29/1054 , H01L29/66795 , H01L29/785
摘要： A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary materials such as layers of InAs and layers of GaSb. The alternating layers of complementary materials provide desirable band gap characteristics for the channel region as a whole that individual layers of material may not.

5. 发明申请

US20160300911A1 Heterostructures for Semiconductor Devices and Methods of Forming the Same 审中-公开
标题翻译：半导体器件的异质结构及其形成方法
公开(公告)号：US20160300911A1
公开(公告)日：2016-10-13
申请号：US15189913
申请日：2016-06-22
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Martin Christopher Holland , Georgios Vellianitis , Richard Kenneth Oxland , Krishna Kumar Bhuwalka , Gerben Doornbos
IPC分类号： H01L29/205 , H01L29/20 , H01L21/02 , H01L29/778 , H01L29/78 , H01L29/10 , H01L29/66
CPC分类号： H01L29/205 , H01L21/02538 , H01L29/1054 , H01L29/20 , H01L29/66545 , H01L29/66795 , H01L29/7787 , H01L29/785
摘要： Various heterostructures and methods of forming heterostructures are disclosed. A method includes removing portions of a substrate to form a temporary fin protruding above the substrate, forming a dielectric material over the substrate and over the temporary fin, removing the temporary fin to form a trench in the dielectric material, the trench exposing a portion of a first crystalline material of the substrate, forming a template material at least partially in the trench, the template material being a second crystalline material that is lattice mismatched to the first crystalline material, forming a barrier material over the template material, the barrier material being a third crystalline material, forming a device material over the barrier material, the device material being a fourth crystalline material, forming a gate stack over the device material, and forming a first source/drain region and a second source/drain region in the device material.
摘要翻译：公开了形成异质结构的各种异质结构和方法。一种方法包括去除衬底的部分以形成在衬底上突出的临时鳍片，在衬底上方并在临时鳍片之上形成介电材料，去除临时鳍片以在电介质材料中形成沟槽，所述衬底的第一结晶材料至少部分地形成在所述沟槽中的模板材料，所述模板材料是与所述第一晶体材料晶格失配的第二结晶材料，在所述模板材料上形成阻挡材料，所述阻挡材料为第三晶体材料，在所述阻挡材料上形成器件材料，所述器件材料是第四晶体材料，在所述器件材料上形成栅叠层，以及在所述器件中形成第一源极/漏极区域和第二源极/漏极区域材料。

6. 发明授权

US09406791B2 Transistors, semiconductor devices, and methods of manufacture thereof 有权
标题翻译：晶体管，半导体器件及其制造方法
公开(公告)号：US09406791B2
公开(公告)日：2016-08-02
申请号：US14977112
申请日：2015-12-21
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Gerben Doornbos , Richard Kenneth Oxland
IPC分类号： H01L29/66 , H01L29/778 , H01L29/205 , H01L21/44 , H01L21/28 , H01L21/3205
CPC分类号： H01L29/7786 , H01L21/182 , H01L29/205 , H01L29/66545 , H01L29/7788 , H01L29/78681
摘要： Transistors, semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a transistor over a workpiece. The transistor includes a sacrificial gate material comprising a group III-V material. The method includes combining a metal (Me) with the group III-V material of the sacrificial gate material to form a gate of the transistor comprising a Me-III-V compound material.
摘要翻译：公开了晶体管，半导体器件及其制造方法。在一个实施例中，制造半导体器件的方法包括在工件上形成晶体管。晶体管包括包含III-V族材料的牺牲栅极材料。该方法包括将金属（Me）与牺牲栅极材料的III-V族材料组合以形成包含Me-III-V复合材料的晶体管的栅极。

7. 发明授权

US09337109B2 Multi-threshold voltage FETs 有权
标题翻译：多阈值电压FET
公开(公告)号：US09337109B2
公开(公告)日：2016-05-10
申请号：US13902326
申请日：2013-05-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Gerben Doornbos , Krishna Kumar Bhuwalka
IPC分类号： H01L29/82 , H01L21/00 , H01L27/092 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/06 , H01L29/10
CPC分类号： H01L21/823821 , H01L21/823412 , H01L27/0605 , H01L27/0924 , H01L29/1054
摘要： A multi-threshold voltage (Vt) field-effect transistor (FET) formed through strain engineering is provided. An embodiment integrated circuit device includes a first transistor including a first channel region over a first buffer, the first channel region formed from a III-V semiconductor material and a second transistor including a second channel region over a second buffer, the second channel region formed from the III-V semiconductor material, the second buffer and the first buffer having a lattice mismatch. A first strain introduced by a lattice mismatch between the III-V semiconductor material and the first buffer is different than a second strain introduced by a lattice mismatch between the III-V semiconductor material and the second buffer. Therefore, the threshold voltage of the first transistor is different than the threshold voltage of the second transistor.
摘要翻译：提供了通过应变工程形成的多阈值电压（Vt）场效应晶体管（FET）。实施例集成电路装置包括：第一晶体管，包括第一缓冲器上的第一沟道区，由III-V半导体材料形成的第一沟道区和在第二缓冲区上包括第二沟道区的第二晶体管，形成第二沟道区从III-V半导体材料，第二缓冲器和第一缓冲器具有晶格失配。由III-V族半导体材料和第一缓冲层之间的晶格失配引入的第一应变与由III-V族半导体材料和第二缓冲层之间的晶格失配导入的第二应变不同。因此，第一晶体管的阈值电压不同于第二晶体管的阈值电压。

8. 发明申请

US20230047356A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
公开(公告)号：US20230047356A1
公开(公告)日：2023-02-16
申请号：US17401323
申请日：2021-08-13
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Oreste Madia , Georgios Vellianitis , Gerben Doornbos , Marcus Johannes Henricus Van Dal
IPC分类号： H01L29/267 , H01L29/51 , H01L21/28 , H01L29/66 , H01L29/78
摘要： A semiconductor device is provided. The semiconductor device includes a gate layer, a semiconductor layer and a ferroelectric layer disposed between the gate layer and the semiconductor layer. The semiconductor layer includes a first material containing a Group III element, a rare-earth element and a Group VI element, the ferroelectric layer includes a second material containing a Group III element, a rare-earth element and a Group V element and the gate layer includes a third material containing a Group III element and a rare-earth element. A method of fabricating a semiconductor device is also provided.

9. 发明申请

US20230041622A1 INTEGRATED CHIP, FERROELECTRIC MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20230041622A1
公开(公告)日：2023-02-09
申请号：US17669378
申请日：2022-02-11
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Oreste Madia , Georgios Vellianitis , Gerben Doornbos , Marcus Johannes Henricus Van Dal
IPC分类号： H01L27/1159 , H01L29/66 , H01L29/78
摘要： A ferroelectric memory device includes a substrate, a gate electrode, a ferroelectric layer, and a pair of source/drain electrodes. The gate electrode is disposed over the substrate. The ferroelectric layer at least covers two adjacent side surfaces of the gate electrode. The pair of source/drain electrodes is over the substrate and disposed on two opposite sides of the gate electrode respectively.

10. 发明授权

US09048122B2 FinFET drive strength modification 有权
标题翻译： FinFET驱动强度修改
公开(公告)号：US09048122B2
公开(公告)日：2015-06-02
申请号：US14329587
申请日：2014-07-11
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Thomas Merelle , Gerben Doornbos , Robert James Lander
IPC分类号： H01L27/088 , H01L21/336 , H01L21/8234 , H01L27/11 , H01L29/66 , H01L29/78
CPC分类号： H01L27/1104 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L27/088 , H01L27/0886 , H01L27/11 , H01L29/0847 , H01L29/6659 , H01L29/66681 , H01L29/66795 , H01L29/7817 , H01L29/7834 , H01L29/785
摘要： A device and method of fabricating the same are disclosed. In an example, a device includes a first fin Field Effect Transistors (finFET) formed on a substrate. The first finFET including a fin formed on the substrate. The device further includes a second finFET formed on the substrate. The first finFET and the second finFET share the fin and wherein the first finFET is without any low density doped (LDD) extension region in the substrate and wherein the second FinFET is associated with a first LDD extension region formed in the substrate such that a drive strength of the second finFET is greater relative to a drive strength of the first finFET.
摘要翻译：公开了一种其制造方法及其制造方法。在一个示例中，器件包括形成在衬底上的第一鳍场效应晶体管（finFET）。第一finFET包括形成在基板上的翅片。该器件还包括形成在衬底上的第二finFET。第一finFET和第二finFET共享翅片，并且其中第一finFET在衬底中没有任何低密度掺杂（LDD）延伸区域，并且其中第二FinFET与在衬底中形成的第一LDD延伸区域相关联，使得驱动器第二finFET的强度相对于第一finFET的驱动强度更大。

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