专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20200044025A1 Melt Anneal Source and Drain Regions 审中-公开
公开(公告)号：US20200044025A1
公开(公告)日：2020-02-06
申请号：US16422123
申请日：2019-05-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Su-Hao Liu , Wen-Yen Chen , Li-Heng Chen , Li-Ting Wang , Liang-Yin Chen , Huicheng Chang , Yee-Chia Yeo , Ying-Lang Wang
IPC分类号： H01L29/08 , H01L29/66 , H01L29/78 , H01L29/161 , H01L21/285 , H01L21/8238 , H01L21/02 , H01L21/265 , H01L27/092
摘要： A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

2. 发明授权

US09768044B2 Apparatus and methods for annealing wafers 有权
公开(公告)号：US09768044B2
公开(公告)日：2017-09-19
申请号：US15138813
申请日：2016-04-26
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
IPC分类号： H01L21/20 , H01L21/36 , H01L21/26 , H01L21/42 , H01L21/4763 , H01L21/00 , H01L21/67 , H01L21/268 , H01L21/324 , B23K26/00 , H01L21/263
CPC分类号： H01L21/67115 , B23K26/352 , H01L21/2636 , H01L21/268 , H01L21/324
摘要： A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.

3. 发明申请

US20160240408A1 Apparatus and Methods for Annealing Wafers 审中-公开
公开(公告)号：US20160240408A1
公开(公告)日：2016-08-18
申请号：US15138813
申请日：2016-04-26
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
IPC分类号： H01L21/67 , H01L21/268 , B23K26/00 , H01L21/263
CPC分类号： H01L21/67115 , B23K26/352 , H01L21/2636 , H01L21/268 , H01L21/324
摘要： A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.

4. 发明申请

US20150044842A1 Integrating Junction Formation of Transistors with Contact Formation 审中-公开
标题翻译：将晶体管的结形成结合到接触形成中
公开(公告)号：US20150044842A1
公开(公告)日：2015-02-12
申请号：US13963911
申请日：2013-08-09
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Li-Ting Wang , Teng-Chun Tsai , Chun-Hsiung Lin , Cheng-Tung Lin , Chi-Yuan Chen , Hong-Mao Lee , Huicheng Chang
IPC分类号： H01L29/66 , H01L21/225 , H01L21/762
CPC分类号： H01L29/665 , H01L21/2254 , H01L21/28518 , H01L21/76224 , H01L29/1054 , H01L29/66545 , H01L29/6659 , H01L29/66651 , H01L29/66803
摘要： A method includes forming a gate stack over a semiconductor region, depositing an impurity layer over the semiconductor region, and depositing a metal layer over the impurity layer. An annealing is then performed, wherein the elements in the impurity layer are diffused into a portion of the semiconductor region by the annealing to form a source/drain region, and wherein the metal layer reacts with a surface layer of the portion of the semiconductor region to form a source/drain silicide region over the source/drain region.
摘要翻译：一种方法包括在半导体区域上形成栅极叠层，在半导体区域上沉积杂质层，以及在杂质层上沉积金属层。然后进行退火，其中通过退火将杂质层中的元素扩散到半导体区域的一部分中以形成源极/漏极区域，并且其中金属层与半导体区域的该部分的表面层反应以在源极/漏极区域上形成源极/漏极硅化物区域。

5. 发明申请

US20140273366A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140273366A1
公开(公告)日：2014-09-18
申请号：US13861247
申请日：2013-04-11
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Cheng-Tung Lin , Teng-Chun Tsai , Li-Ting Wang , Chi-Yuan Chen , Kuo-Yin Lin , Wan-Chun Pan , Ming-Liang Yen , Ching-Wei Tsai , Kuo-Cheng Ching , Huicheng Chang , Chih-Hao Wang
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L27/092 , H01L21/285 , H01L21/28512 , H01L21/28518 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L21/76855 , H01L21/823418 , H01L21/823814 , H01L21/8258 , H01L23/485 , H01L27/0629 , H01L27/088 , H01L27/0928 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including an n-type field effect transistor (N-FET) region, a p-type FET (P-FET) region, and an insulating material disposed over the N-FET region and the P-FET region. The method includes patterning the insulating material to expose a portion of the N-FET region and a portion of the P-FET region, and forming an oxide layer over the exposed portion of the N-FET region and the exposed portion of the P-FET region. The oxide layer over the P-FET region is altered, and a metal layer is formed over a portion of the N-FET region and the P-FET region. The workpiece is annealed to form a metal-insulator-semiconductor (MIS) tunnel diode over the N-FET region and a silicide or germinide material over the P-FET region.
摘要翻译：公开了半导体器件及其制造方法。在一些实施例中，制造半导体器件的方法包括提供包括n型场效应晶体管（N-FET）区域，p型FET（P-FET）区域和设置在N上的绝缘材料的工件 -FET区域和P-FET区域。该方法包括图案化绝缘材料以暴露N-FET区域的一部分和P-FET区域的一部分，并且在N-FET区域的暴露部分上形成氧化物层，并且P- FET区域。改变P-FET区域上的氧化物层，并且在N-FET区域和P-FET区域的一部分上形成金属层。工件被退火以在N-FET区域上形成金属 - 绝缘体半导体（MIS）隧道二极管，并在P-FET区域上形成硅化物或发芽体材料。

6. 发明授权

US08772056B2 Dummy pattern design for thermal annealing 有权
标题翻译：用于热退火的假模式设计
公开(公告)号：US08772056B2
公开(公告)日：2014-07-08
申请号：US14134344
申请日：2013-12-19
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Li-Ting Wang , Jiunn-Ren Hwang
IPC分类号： H01L21/00
CPC分类号： H01L21/324 , H01L27/0207 , H01L27/11
摘要： The present disclosure provides a semiconductor structure including a semiconductor substrate having a device region and a dummy region adjacent the device region; a plurality of active regions in the device region; and a plurality of dummy active regions in the dummy region, where each of the active regions has a first dimension in a first direction and a second dimension in a second direction perpendicular to the first direction, and the first dimension is substantially greater than the second dimension; and each of the dummy active regions has a third dimension in the first direction and a fourth dimension in the second direction, and the third dimension is substantially greater than the fourth dimension. The plurality of dummy active regions are configured such that thermal annealing effect in the dummy region is substantially equal to that of the device region.
摘要翻译：本公开提供了一种半导体结构，其包括具有器件区域和邻近器件区域的虚设区域的半导体衬底; 所述器件区域中的多个有源区; 以及所述虚拟区域中的多个虚拟有源区域，其中所述有源区域中的每一个具有在第一方向上的第一尺寸和与所述第一方向垂直的第二方向上的第二尺寸，并且所述第一尺寸基本上大于所述第二尺寸尺寸; 并且所述虚拟有源区域中的每一个具有在所述第一方向上的第三尺寸和在所述第二方向上的第四尺寸，并且所述第三尺寸基本上大于所述第四尺寸。多个虚拟有源区域被配置为使得虚拟区域中的热退火效应基本上等于器件区域的热退火效果。

7. 发明申请

US20220173239A1 Source/Drain Structure 有权
公开(公告)号：US20220173239A1
公开(公告)日：2022-06-02
申请号：US17651437
申请日：2022-02-17
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Su-Hao Liu , Kuo-Ju Chen , Wen-Yen Chen , Ying-Lang Wang , Liang-Yin Chen , Li-Ting Wang , Huicheng Chang
IPC分类号： H01L29/78 , H01L29/66 , H01L21/02 , H01L21/768 , H01L21/8238 , H01L21/324
摘要： Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

8. 发明授权

US11594636B2 Source/drain structure 有权
公开(公告)号：US11594636B2
公开(公告)日：2023-02-28
申请号：US17651437
申请日：2022-02-17
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Su-Hao Liu , Kuo-Ju Chen , Wen-Yen Chen , Ying-Lang Wang , Liang-Yin Chen , Li-Ting Wang , Huicheng Chang
IPC分类号： H01L29/66 , H01L29/78 , H01L21/02 , H01L21/768 , H01L21/8238 , H01L21/324
摘要： Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

9. 发明授权

US11257952B2 Source/drain structure 有权
公开(公告)号：US11257952B2
公开(公告)日：2022-02-22
申请号：US16876436
申请日：2020-05-18
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Su-Hao Liu , Kuo-Ju Chen , Wen-Yen Chen , Ying-Lang Wang , Liang-Yin Chen , Li-Ting Wang , Huicheng Chang
IPC分类号： H01L29/78 , H01L29/66 , H01L21/02 , H01L21/768 , H01L21/8238 , H01L21/324
摘要： Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

10. 发明授权

US10978344B2 Melting laser anneal of epitaxy regions 有权
公开(公告)号：US10978344B2
公开(公告)日：2021-04-13
申请号：US16549213
申请日：2019-08-23
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Su-Hao Liu , Wen-Yen Chen , Tz-Shian Chen , Cheng-Jung Sung , Li-Ting Wang , Liang-Yin Chen , Huicheng Chang , Yee-Chia Yeo , Syun-Ming Jang
IPC分类号： H01L21/768 , H01L21/02 , H01L29/78 , H01L29/66 , H01L29/08
摘要： A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式