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1. 发明授权

US11184017B2 Method and circuit for noise shaping SAR analog-to-digital converter 有权
公开(公告)号：US11184017B2
公开(公告)日：2021-11-23
申请号：US17020219
申请日：2020-09-14
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Martin Kinyua
IPC分类号： H03M1/06 , H03M1/00 , H03M3/00 , H03M1/12 , H03M1/46
摘要： An analog-to-digital (A/D) conversion system includes a track-and-hold circuit, a comparison circuit, a control circuit, a digital-to-analog (D/A) conversion circuit, a switched buffer and a loop filter. The track-and-hold circuit is configured to output a first signal based on an input signal or a first timing signal. The comparison circuit is configured to generate a comparison result based on the first signal and a filtered residue signal. The control circuit is coupled to the comparison circuit, and is configured to generate an N-bit logical signal according to N comparison results from the comparison circuit. The D/A circuit is configured to generate a feedback signal based on the N-bit logical signal. The switched buffer is configured to generate a first error signal based on a second timing signal and a second error signal. The loop filter is configured to generate the filtered residue signal based on the first error signal.

2. 发明申请

US20210305996A1 ANALOG TO DIGITAL CONVERTER WITH VCO-BASED AND PIPELINED QUANTIZERS 有权
公开(公告)号：US20210305996A1
公开(公告)日：2021-09-30
申请号：US17181381
申请日：2021-02-22
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Martin Kinyua , Eric Soenen
IPC分类号： H03M3/00 , H03K3/03
摘要： An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.

3. 发明申请

US20210234549A1 ANALOG TO DIGITAL CONVERTER WITH INVERTER BASED AMPLIFIER 有权
公开(公告)号：US20210234549A1
公开(公告)日：2021-07-29
申请号：US17227949
申请日：2021-04-12
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Martin Kinyua
IPC分类号： H03M1/46 , H03M1/12 , H03F3/45
摘要： An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and a first analog residue signal corresponding to a difference between the first digital value and the analog input signal. An inverter based residue amplifier is configured to receive the first analog residue signal, amplify the first analog residue signal, and output an amplified residue signal. The amplified residue signal is converted to a second digital value, and the first and second digital values are combined to create a digital output signal corresponding to the analog input voltage signal.

4. 发明申请

US20210099184A1 ANALOG TO DIGITAL CONVERTER WITH CURRENT STEERING STAGE 有权
公开(公告)号：US20210099184A1
公开(公告)日：2021-04-01
申请号：US17120438
申请日：2020-12-14
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Martin Kinyua , Eric Soenen
IPC分类号： H03M1/14 , H03M1/06 , H03M1/16
摘要： An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.

5. 发明申请

US20200099386A1 ANALOG TO DIGITAL CONVERTER 审中-公开
公开(公告)号：US20200099386A1
公开(公告)日：2020-03-26
申请号：US16684163
申请日：2019-11-14
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Martin Kinyua
IPC分类号： H03M1/34 , H03M1/14
摘要： An analog-to-digital converter (“ADC”) has an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal. A second ADC stage is coupled to the first ADC stage and is configured to convert the analog residue signal to a second digital value. At least one of the first ADC stage and the second ADC stage includes a first sub-stage configured to convert an analog signal to a first number of bits of a digital value representing the analog signal, and a second sub-stage configured to convert the analog signal to a second number of bits of the digital value, where the second number of bits is greater than the first number of bits. A controller is coupled to the first and second ADC stages and configured to combine the first digital value and the second digital value into a digital output signal representing the analog input voltage signal.

6. 发明申请

US20220368340A1 ANALOG TO DIGITAL CONVERTER WITH VCO-BASED AND PIPELINED QUANTIZERS 有权
公开(公告)号：US20220368340A1
公开(公告)日：2022-11-17
申请号：US17876761
申请日：2022-07-29
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Martin Kinyua , Eric Soenen
IPC分类号： H03M3/00 , H03K3/03
摘要： An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.

7. 发明申请

US20220368292A1 AMPILFIER WITH VCO-BASED ADC 有权
公开(公告)号：US20220368292A1
公开(公告)日：2022-11-17
申请号：US17869111
申请日：2022-07-20
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Martin Kinyua , Eric Soenen
IPC分类号： H03F3/217 , H03F3/185 , H03M3/00 , H03F1/02
摘要： An amplifier includes an input circuit configured to receive an analog input signal and a feedback signal, and output an analog error signal based on the analog input signal and the feedback signal. An ADC is configured to convert the analog error signal into a digital signal in a phase domain. A digital control circuit is configured to generate a digital control signal based on the digital signal in the phase domain. An output circuit is configured to generate an amplified output signal based on the digital control signal, and a feedback circuit is configured generate the feedback signal based on the amplified output signal.

8. 发明申请

US20220239307A1 ANALOG TO DIGITAL CONVERTER WITH CURRENT MODE STAGE 有权
公开(公告)号：US20220239307A1
公开(公告)日：2022-07-28
申请号：US17717519
申请日：2022-04-11
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Martin Kinyua , Eric Soenen
IPC分类号： H03M1/14 , H03M1/06 , H03M1/16
摘要： An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current mode DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.

9. 发明申请

US20190103879A1 ANALOG TO DIGITAL CONVERTER 审中-公开
公开(公告)号：US20190103879A1
公开(公告)日：2019-04-04
申请号：US16206159
申请日：2018-11-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Martin Kinyua
IPC分类号： H03M1/34 , H03M1/14
摘要： An analog-to-digital converter (“ADC”) has an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal. A second ADC stage is coupled to the first ADC stage and is configured to convert the analog residue signal to a second digital value. At least one of the first ADC stage and the second ADC stage includes a first sub-stage configured to convert an analog signal to a first number of bits of a digital value representing the analog signal, and a second sub-stage configured to convert the analog signal to a second number of bits of the digital value, where the second number of bits is greater than the first number of bits. A controller is coupled to the first and second ADC stages and configured to combine the first digital value and the second digital value into a digital output signal representing the analog input voltage signal.

10. 发明授权

US09287892B2 Noise shaping for digital pulse-width modulators 有权
标题翻译：数字脉宽调制器的噪声整形
公开(公告)号：US09287892B2
公开(公告)日：2016-03-15
申请号：US14691084
申请日：2015-04-20
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Eric Soenen , Alan Roth , Martin Kinyua , Justin Shi , Justin Gaither
IPC分类号： H03M3/00 , H03H17/00
CPC分类号： H03M3/344 , H03H17/00 , H03M3/00 , H03M3/464
摘要： A circuit includes an analog-to-digital converter (ADC). The ADC is configured to receive an analog feedback signal and an analog input signal and generate a digital output. The circuit further includes a digital filter configured to filter the digital output and a noise shaper. The noise shaper is configured to truncate the filtered digital output and generate a noise shaper output, and to shape quantization noise generated during truncation. The circuit further includes a pulse width modulation digital-to-analog converter (PWM DAC) configured to process the truncated digital output of the noise shaper output and generate a PWM DAC output.
摘要翻译：电路包括模数转换器（ADC）。 ADC配置为接收模拟反馈信号和模拟输入信号并产生数字输出。电路还包括被配置为对数字输出进行滤波的数字滤波器和噪声整形器。噪声整形器被配置为截断滤波的数字输出并产生噪声整形器输出，并且形成在截断期间产生的量化噪声。电路还包括脉冲宽度调制数模转换器（PWM DAC），其被配置为处理噪声整形器输出的截断数字输出并产生PWM DAC输出。

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