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1. 发明申请

US20210296471A1 Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same 有权
公开(公告)号：US20210296471A1
公开(公告)日：2021-09-23
申请号：US17322512
申请日：2021-05-17
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Harry-Hay-Lay Chuang , Cheng-Cheng Kuo , Ming Zhu
IPC分类号： H01L29/66 , H01L29/739 , H01L29/06 , H01L29/78
摘要： A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature.

2. 发明申请

US20200020788A1 Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same 审中-公开
公开(公告)号：US20200020788A1
公开(公告)日：2020-01-16
申请号：US16579110
申请日：2019-09-23
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Harry-Hak-Lay Chuang , Cheng-Cheng Kuo , Ming Zhu
IPC分类号： H01L29/66 , H01L29/739 , H01L29/06 , H01L29/78
摘要： A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature.

3. 发明授权

US09525040B2 Method of fabricating hybrid impact-ionization semiconductor device 有权
标题翻译：制造混合冲击电离半导体器件的方法
公开(公告)号：US09525040B2
公开(公告)日：2016-12-20
申请号：US14188181
申请日：2014-02-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ming Zhu , Lee-Wee Teo , Harry Hak-Lay Chuang
IPC分类号： H01L21/336 , H01L29/66 , H01L29/423 , H01L29/739 , H01L21/8238
CPC分类号： H01L29/66484 , H01L21/823807 , H01L29/423 , H01L29/7391
摘要： A method includes providing a semiconductor substrate having an active region and forming an isolation structure to isolate the active region. First and second gate structures are formed over the active region. First and second doped regions are formed within the active region of the substrate, the first doped region has a first conductivity type, the second doped region has the second conductivity type. The first and second gate structures are interposed between the first and second doped regions.
摘要翻译：一种方法包括提供具有活性区域并形成隔离结构以隔离有源区的半导体衬底。第一和第二栅极结构形成在有源区上。第一和第二掺杂区形成在衬底的有源区内，第一掺杂区具有第一导电类型，第二掺杂区具有第二导电类型。第一和第二栅极结构被插入在第一和第二掺杂区域之间。

4. 发明授权

US09337194B2 Semiconductor device and method of forming the same 有权
公开(公告)号：US09337194B2
公开(公告)日：2016-05-10
申请号：US14617409
申请日：2015-02-09
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Harry-Hak-Lay Chuang , Ming Zhu
IPC分类号： H01L21/70 , H01L27/092 , H01L21/8238 , H01L21/322 , H01L29/66 , H01L29/78 , H01L29/04 , H01L29/08 , H01L21/266 , H01L21/324 , H01L21/8234 , H01L29/49
CPC分类号： H01L27/092 , H01L21/266 , H01L21/322 , H01L21/324 , H01L21/823412 , H01L21/823807 , H01L21/823814 , H01L29/045 , H01L29/0847 , H01L29/495 , H01L29/4966 , H01L29/66545 , H01L29/66636 , H01L29/78 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device includes a first NMOS device with a first threshold voltage and a second NMOS device with a second threshold voltage. The first NMOS device includes a first gate structure over a semiconductor substrate, first source/drain (S/D) regions in the semiconductor substrate and adjacent to opposite edges of the first gate structure. The first S/D regions are free of dislocation. The second NMOS device includes a second gate structure over the semiconductor substrate, second S/D regions in the semiconductor substrate and adjacent to opposite edges of the second gate structure, and a dislocation in the second S/D regions.

5. 发明授权

US09299696B2 Semiconductor structure with suppressed STI dishing effect at resistor region 有权
标题翻译：在电阻器区域具有抑制的STI凹陷效应的半导体结构
公开(公告)号：US09299696B2
公开(公告)日：2016-03-29
申请号：US14221466
申请日：2014-03-21
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Harry-Hak-Lay Chuang , Ming Zhu , Lee-Wee Teo , Bao-Ru Young
IPC分类号： H01L27/06 , H01L21/3105 , H01L21/311 , H01L21/762 , H01L29/06 , H01L49/02
CPC分类号： H01L27/0629 , H01L21/31055 , H01L21/31111 , H01L21/76224 , H01L28/20 , H01L29/0649
摘要： An integrated circuit includes a semiconductor substrate; a first shallow trench isolation (STI) feature of a first width and a second STI feature of a second width in a semiconductor substrate. The first width is less than the second width. The first STI feature has an etch-resistance less than that of the second STI feature.
摘要翻译：集成电路包括半导体衬底; 半导体衬底中第一宽度的第一浅沟槽隔离（STI）特征和第二宽度的第二STI特征。第一宽度小于第二宽度。第一STI特征具有小于第二STI特征的耐蚀刻性。

6. 发明申请

US20160064524A1 VERTICAL TUNNELING FIELD-EFFECT TRANSISTOR CELL AND FABRICATING THE SAME 有权
标题翻译：垂直隧道场效应晶体管和制造它们
公开(公告)号：US20160064524A1
公开(公告)日：2016-03-03
申请号：US14937445
申请日：2015-11-10
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Harry-Hak-Lay Chuang , Cheng-Cheng Kuo , Chi-Wen Liu , Ming Zhu
IPC分类号： H01L29/66 , H01L29/417
CPC分类号： H01L29/66666 , H01L29/0676 , H01L29/41775 , H01L29/66356 , H01L29/7391
摘要： A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A gate stack is disposed over the substrate. The gate stack has a planar portion, which is parallel to the surface of substrate and a gating surface, which wraps around a middle portion of the frustoconical protrusion structure, including overlapping with the raised drain region. An isolation dielectric layer is disposed between the planar portion of the gate stack and the drain region. A source region is disposed as a top portion of the frustoconical protrusion structure, including overlapping with a top portion of the gating surface of the gate stack.
摘要翻译：公开了隧道场效应晶体管（TFET）器件。截头圆锥形突起结构设置在衬底上并突出到衬底平面之外。漏极区域设置在与截头圆锥形突起结构相邻的衬底上，并延伸到截头圆锥形突起结构的底部作为升高的漏极区域。栅极堆叠设置在衬底上。栅极堆叠具有平行于衬底的表面的平坦部分和围绕截头圆锥形突出结构的中间部分包围的浇口表面，包括与凸起的漏极区域重叠。隔离电介质层设置在栅极堆叠的平面部分和漏极区之间。源极区域被设置为截头圆锥形突起结构的顶部，包括与栅极叠层的栅极表面的顶部重叠。

7. 发明申请

US20150364459A1 N/P BOUNDARY EFFECT REDUCTION FOR METAL GATE TRANSISTORS 有权
标题翻译： N / P边界效应减少金属栅极晶体管
公开(公告)号：US20150364459A1
公开(公告)日：2015-12-17
申请号：US14837016
申请日：2015-08-27
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Hak-Lay Chuang , Cheng-Cheng Kuo , Ching-Che Tsai , Ming Zhu , Bao-Ru Young
IPC分类号： H01L27/02 , H01L29/423 , H01L29/417 , H01L27/092
CPC分类号： H01L27/0207 , H01L21/0274 , H01L21/28123 , H01L21/32139 , H01L21/823456 , H01L27/092 , H01L29/41775 , H01L29/42356 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： The present disclosure provides a semiconductor device. A first active region is formed in a substrate. The first active region is elongated in a first direction in a top view. A first gate is formed over the substrate. The first gate is elongated in a second direction in the top view. A portion of the first gate is located over the first active region. A second gate is formed over the substrate. The second gate is elongated in the second direction in the top view. A portion of the second gate is located over the first active region. The second gate is shorter than the first gate in the second direction.
摘要翻译：本发明提供一种半导体器件。在衬底中形成第一有源区。第一有源区域在顶视图中沿第一方向伸长。第一栅极形成在衬底上。第一个门在顶视图中沿第二个方向伸长。第一栅极的一部分位于第一有源区上方。第二栅极形成在衬底上。第二个门在俯视图中沿第二个方向伸长。第二栅极的一部分位于第一有源区上方。第二栅极在第二方向上比第一栅极短。

8. 发明申请

US20150357445A1 STRUCTURE AND METHOD FOR VERTICAL TUNNELING FIELD EFFECT TRANSISTOR WITH LEVELED SOURCE AND DRAIN 审中-公开
标题翻译：垂直隧道的结构与方法，具有水平源和漏水的场效应晶体管
公开(公告)号：US20150357445A1
公开(公告)日：2015-12-10
申请号：US14827464
申请日：2015-08-17
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Harry-Hak-Lay Chuang , Yi-Ren Chen , Chi-Wen Liu , Chao-Hsiung Wang , Ming Zhu
IPC分类号： H01L29/66 , H01L21/265 , H01L29/08
CPC分类号： H01L29/66977 , H01L21/823487 , H01L21/823885 , H01L27/0802 , H01L27/092 , H01L28/20 , H01L29/0676 , H01L29/66356 , H01L29/66666 , H01L29/7391
摘要： The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.
摘要翻译：本公开提供了半导体结构的一个实施例。半导体结构包括具有第一区域和第二区域的半导体衬底; 形成在所述第一区域内的所述半导体衬底上的第一半导体台面; 在所述第二区域中形成在所述半导体衬底上的第二半导体台面; 以及形成在半导体衬底上的场效应晶体管（FET）。 FET包括形成在第一半导体台面的顶部的第一导电类型的第一掺杂特征; 形成在第一半导体台面的底部部分中的第二导电类型的第二掺杂特征，第二半导体台面以及在第一和第二半导体台面之间的半导体衬底的一部分; 在所述第一半导体台面的中间部分中的沟道，并且介于所述源极和漏极之间; 以及形成在第一半导体台面的侧壁上的栅极。

9. 发明授权

US09123745B2 Device with a vertical gate structure 有权
标题翻译：具有垂直栅极结构的器件
公开(公告)号：US09123745B2
公开(公告)日：2015-09-01
申请号：US14268817
申请日：2014-05-02
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Harry-Hak-Lay Chuang , Ming Zhu , Yi-Ren Chen
IPC分类号： H01L21/336 , H01L29/66 , H01L21/28 , H01L29/423 , H01L21/8238 , H01L21/768
CPC分类号： H01L29/66795 , H01L21/28114 , H01L21/76885 , H01L21/823821 , H01L21/823828 , H01L21/823885 , H01L29/42376
摘要： A device includes a wafer substrate, a conical frustum structure formed in the wafer substrate, and a gate all-around (GAA) structure circumscribing the middle portion of the conical frustum structure. The conical frustum structure includes a drain formed at a bottom portion of the conical frustum, a source formed at a top portion of the vertical conical frustum, and a channel formed at a middle portion of the conical frustum connecting the source and the drain. The GAA structure overlaps with the source at one side of the GAA structure, crosses over the channel, and overlaps with the drain at another side of the GAA structure.
摘要翻译：一种器件包括晶片衬底，形成在晶片衬底中的锥形截头锥体结构，以及围绕锥形截头锥体结构的中间部分的栅极全能（GAA）结构。锥形截头锥体结构包括形成在锥形截头锥体的底部处的排水口，形成在垂直锥形截头锥体的顶部处的源和形成在连接源极和漏极的锥形截头锥体的中间部分处的通道。 GAA结构与GAA结构一侧的源重叠，与沟道交叉，并与GAA结构另一侧的漏极重叠。

10. 发明申请

US20150054065A1 Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same 有权
标题翻译：垂直隧道场效应晶体管电池及其制造
公开(公告)号：US20150054065A1
公开(公告)日：2015-02-26
申请号：US14532571
申请日：2014-11-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Harry-Hak-Lay Chuang , Cheng-Cheng Kuo , Ming Zhu
IPC分类号： H01L27/088 , H01L29/66 , H01L29/417 , H01L29/78 , H01L29/06
CPC分类号： H01L27/088 , H01L21/70 , H01L21/823487 , H01L29/0657 , H01L29/41783 , H01L29/66356 , H01L29/66666 , H01L29/66977 , H01L29/7391 , H01L29/7827
摘要： A method of making a tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A source region is formed as a top portion of the frustoconical protrusion structure. A series connection and a parallel connection are made among TFET devices units.
摘要翻译：公开了一种制造隧道场效应晶体管（TFET）器件的方法。截头圆锥形突起结构设置在衬底上并突出到衬底平面之外。在基板上形成隔离特征。漏极区域设置在与截头圆锥形突起结构相邻的衬底上，并延伸到截头圆锥形突起结构的底部作为升高的漏极区域。源区域形成为截头圆锥形突起结构的顶部。在TFET器件单元之间进行串联和并联连接。

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