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1. 发明授权

US11239365B2 Structure and method for providing line end extensions for fin-type active regions 有权
公开(公告)号：US11239365B2
公开(公告)日：2022-02-01
申请号：US16726405
申请日：2019-12-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shao-Ming Yu , Chang-Yun Chang , Chih-Hao Chang , Hsin-Chih Chen , Kai-Tai Chang , Ming-Feng Shieh , Kuei-Liang Lu , Yi-Tang Lin
IPC分类号： H01L29/78 , H01L29/66 , H01L21/8234 , H01L21/67 , H01L27/088
摘要： A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

2. 发明授权

US09953975B2 Methods for forming STI regions in integrated circuits 有权
公开(公告)号：US09953975B2
公开(公告)日：2018-04-24
申请号：US13946660
申请日：2013-07-19
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chih-Yu Hsu , Yi-Tang Lin , Clement Hsinjen Wann , Chih-Sheng Chang , Wei-Chun Tsai , Jyh-Cherng Sheu , Chi-Yuan Shih
IPC分类号： H01L29/49 , H01L27/088 , H01L21/8234 , H01L21/762
CPC分类号： H01L27/0886 , H01L21/76224 , H01L21/823425 , H01L21/823481
摘要： A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.

3. 发明授权

US09553025B2 Selective Fin-shaping process 有权
标题翻译：选择性鳍形成过程
公开(公告)号：US09553025B2
公开(公告)日：2017-01-24
申请号：US14598276
申请日：2015-01-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Clement Hsingjen Wann , Ling-Yen Yeh , Chi-Yuan Shih , Yi-Tang Lin , Chih-Sheng Chang , Chi-Wen Liu
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/84 , H01L29/78 , H01L27/088 , H01L27/092 , H01L27/12 , H01L29/06 , H01L21/265 , H01L21/311 , H01L21/762 , H01L29/66
CPC分类号： H01L21/823431 , H01L21/265 , H01L21/31111 , H01L21/76224 , H01L21/823481 , H01L21/823821 , H01L21/845 , H01L27/088 , H01L27/0924 , H01L27/1211 , H01L29/06 , H01L29/66818 , H01L29/78 , H01L29/7853 , H01L29/7854
摘要： A method of forming a fin field-effect transistor (FinFET) includes forming a plurality of fins on a substrate. The method further includes forming an oxide layer on the substrate, wherein a bottom portion of each fin of the plurality of fins is embedded in the oxide layer, and the bottom portion of each fin of the plurality of fins has substantially a same shape. The method further includes shaping at least one fin of the plurality of fins, wherein a top portion of the at least one fin has a different shape from a top portion of another fin of the plurality of fins.
摘要翻译：形成鳍状场效应晶体管（FinFET）的方法包括在基板上形成多个翅片。所述方法还包括在所述基板上形成氧化物层，其中所述多个翅片的每个翅片的底部嵌入所述氧化物层中，并且所述多个翅片的每个翅片的底部具有基本相同的形状。所述方法还包括成形所述多个翅片中的至少一个翅片，其中，所述至少一个翅片的顶部与所述多个翅片中的另一翅片的顶部具有不同的形状。

4. 发明授权

US08875076B2 System and methods for converting planar design to FinFET design 有权
标题翻译：将平面设计转换为FinFET设计的系统和方法
公开(公告)号：US08875076B2
公开(公告)日：2014-10-28
申请号：US14229134
申请日：2014-03-28
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yi-Tang Lin , Cheok-Kei Lei , Shu-Yu Chen , Yu-Ning Chang , Hsiao-Hui Chen , Chih-Sheng Chang , Chien-Wen Chen , Clement Hsingjen Wann
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5068 , H01L21/823821 , H01L27/0207
摘要： A method and layout generating machine for generating a layout for a device having FinFETs from a first layout for a device having planar transistors are disclosed. A planar layout with a plurality of FinFET active areas is received and corresponding FinFET active areas are generated with active area widths. Mandrels are generated according to the active area widths and adjusted such that a beta ratio of a beta number for each FinFET active area to a beta number for each corresponding planar active area is within a predetermined beta ratio range.
摘要翻译：公开了一种用于从具有平面晶体管的器件的第一布局生成具有FinFET的器件的布局的方法和布局生成机。接收具有多个FinFET有源区域的平面布局，并且生成具有有效面积宽度的对应的FinFET有源区域。根据有效面积宽度产生心轴，并且被调整为使得每个对应的平面有源区域的每个FinFET有源区域的β数目与β数量的β比率在预定的β比范围内。

5. 发明申请

US20180337198A1 SYSTEMS AND METHODS FOR A SEMICONDUCTOR STRUCTURE HAVING MULTIPLE SEMICONDUCTOR-DEVICE LAYERS 审中-公开
公开(公告)号：US20180337198A1
公开(公告)日：2018-11-22
申请号：US16051280
申请日：2018-07-31
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yi-Tang Lin , Chun-Hsiung Tsai , Clement Hsingjen Wann
IPC分类号： H01L27/12 , H01L27/092 , H01L29/10 , H01L21/762 , H01L21/84 , H01L21/8238 , H01L29/165
CPC分类号： H01L27/1207 , H01L21/76254 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/092 , H01L27/1211 , H01L29/1054 , H01L29/165
摘要： A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the first channel material is different from the lattice constant of the bulk substrate to introduce strain to the first channel material. The method further comprises fabricating a first semiconductor device layer on the bulk substrate with the strained first channel material, fabricating a buffer layer comprising dielectric material with a blanket top surface above the first semiconductor layer, bonding to the blanket top surface a bottom surface of a second substrate comprising a buried oxide with a second channel material above the buried oxide, and fabricating a second semiconductor device layer on the second substrate.

6. 发明授权

US09673328B2 Structure and method for providing line end extensions for fin-type active regions 有权
公开(公告)号：US09673328B2
公开(公告)日：2017-06-06
申请号：US14586602
申请日：2014-12-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shao-Ming Yu , Chang-Yun Chang , Chih-Hao Chang , Hsin-Chih Chen , Kai-Tai Chang , Ming-Feng Shieh , Kuei-Liang Lu , Yi-Tang Lin
IPC分类号： H01L29/49 , H01L29/78 , H01L27/088 , H01L29/66 , H01L21/67 , H01L21/8234
CPC分类号： H01L29/785 , H01L21/67248 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L29/66545 , H01L29/66795 , H01L29/7842
摘要： A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

7. 发明授权

US09029958B2 FinFETs and the methods for forming the same 有权
标题翻译： FinFET及其形成方法
公开(公告)号：US09029958B2
公开(公告)日：2015-05-12
申请号：US13914362
申请日：2013-06-10
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chia-Cheng Ho , Tzu-Chiang Chen , Yi-Tang Lin , Chih-Sheng Chang
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method includes forming a gate stack including a gate electrode on a first semiconductor fin. The gate electrode includes a portion over and aligned to a middle portion of the first semiconductor fin. A second semiconductor fin is on a side of the gate electrode, and does not extend to under the gate electrode. The first and the second semiconductor fins are spaced apart from, and parallel to, each other. An end portion of the first semiconductor fin and the second semiconductor fin are etched. An epitaxy is performed to form an epitaxy region, which includes a first portion extending into a first space left by the etched first end portion of the first semiconductor fin, and a second portion extending into a second space left by the etched second semiconductor fin. A first source/drain region is formed in the epitaxy region.
摘要翻译：一种方法包括在第一半导体鳍上形成包括栅电极的栅叠层。栅极电极包括在第一半导体鳍片的中间部分上并对准的部分。第二半导体鳍片位于栅电极的一侧，并且不延伸至栅电极下方。第一和第二半导体散热片彼此间隔开并平行。蚀刻第一半导体鳍片和第二半导体鳍片的端部。进行外延以形成外延区域，其包括延伸到由第一半导体鳍片的蚀刻的第一端部分留下的第一空间的第一部分和延伸到由蚀刻的第二半导体鳍留下的第二空间的第二部分。在外延区域形成第一源极/漏极区域。

8. 发明授权

US09026959B2 Method and device for increasing fin device density for unaligned fins 有权
标题翻译：用于增加未对准翅片翅片装置密度的方法和装置
公开(公告)号：US09026959B2
公开(公告)日：2015-05-05
申请号：US14334195
申请日：2014-07-17
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chien-Hsun Wang , Chih-Sheng Chang , Yi-Tang Lin , Ming-Feng Shieh
IPC分类号： G06F17/50 , H01L29/66 , G03F1/00
CPC分类号： G06F17/5072 , G03F1/00 , G06F17/5068 , H01L29/66795
摘要： A semiconductor manufacturing method of generating a layout for a device includes defining a first plurality of mandrels in a first active region of a first layout. Each mandrel of the first plurality of mandrels extends in a first direction and being spaced apart in a second direction perpendicular to the first direction. The method further includes defining a second plurality of mandrels in a second active region of the first layout. Each mandrel of the second plurality of mandrels extends in the first direction and being spaced apart in the second direction. An edge of the first active region is spaced from an edge of the second active region by a minimum distance less than a specified minimum spacing. The method further includes connecting, using a layout generator, at least one mandrel of the first plurality of mandrels to a corresponding mandrel of the second plurality of mandrels.
摘要翻译：产生装置的布局的半导体制造方法包括在第一布局的第一有源区中限定第一多个心轴。第一多个心轴的每个心轴在第一方向上延伸并且在垂直于第一方向的第二方向上间隔开。该方法还包括在第一布局的第二活动区域中限定第二多个心轴。第二多个心轴的每个心轴在第一方向上延伸并且在第二方向上间隔开。第一有源区域的边缘与第二有源区域的边缘间隔小于指定的最小间隔的最小距离。该方法还包括使用布局发生器将第一多个心轴中的至少一个心轴连接到第二多个心轴的对应心轴。

9. 发明授权

US10573751B2 Structure and method for providing line end extensions for fin-type active regions 有权
公开(公告)号：US10573751B2
公开(公告)日：2020-02-25
申请号：US15614439
申请日：2017-06-05
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shao-Ming Yu , Chang-Yun Chang , Chih-Hao Chang , Hsin-Chih Chen , Kai-Tai Chang , Ming-Feng Shieh , Kuei-Liang Lu , Yi-Tang Lin
IPC分类号： H01L29/78 , H01L29/66 , H01L21/8234 , H01L21/67 , H01L27/088
摘要： A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

10. 发明授权

US09472672B2 Eliminating fin mismatch using isolation last 有权
标题翻译：消除鳍不匹配，最后使用隔离
公开(公告)号：US09472672B2
公开(公告)日：2016-10-18
申请号：US14017564
申请日：2013-09-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yi-Tang Lin , Chih-Yu Hsu , Clement Hsingjen Wann , Chih-Sheng Chang
IPC分类号： H01L29/78 , H01L29/66 , H01L21/76 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12
CPC分类号： H01L29/785 , H01L21/76 , H01L21/76224 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/6681
摘要： An embodiment fin field-effect transistor (FinFET) includes an inner fin, and outer fin spaced apart from the inner fin by a shallow trench isolation (STI) region, an isolation fin spaced apart from the outer fin by the STI region, the isolation fin including a body portion, an isolation oxide, and an etch stop layer, the etch stop layer interposed between the body portion and the isolation oxide and between the STI region and the isolation oxide, and a gate formed over the inner fin, the outer fin, and the isolation fin.
摘要翻译：实施例的鳍状场效应晶体管（FinFET）包括通过浅沟槽隔离（STI）区域与内部鳍片间隔开的内部翅片和外部翅片，由STI区域与外部翅片间隔开的隔离翅片，隔离件翅片，其包括主体部分，隔离氧化物和蚀刻停止层，所述蚀刻停止层插入在主体部分和隔离氧化物之间以及STI区域和隔离氧化物之间，以及形成在内部翅片上的栅极，外部鳍和隔离鳍。

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