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1. 发明授权

US12027475B2 Semiconductor die including guard ring structure and three-dimensional device structure including the same 有权
公开(公告)号：US12027475B2
公开(公告)日：2024-07-02
申请号：US18338596
申请日：2023-06-21
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Jen-Yuan Chang , Chien-Chang Lee , Chia-Ping Lai
IPC分类号： H01L21/00 , H01L21/768 , H01L23/48 , H01L23/522 , H01L23/58 , H01L25/065 , H01L23/00 , H01L25/18
CPC分类号： H01L23/585 , H01L21/76898 , H01L23/481 , H01L23/5222 , H01L25/0657 , H01L23/562 , H01L25/18 , H01L2225/06544
摘要： A die includes: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate and including: inter-metal dielectric (IMD) layers; metal features embedded in the IMD layers; and a guard ring structure including concentric first and second guard rings that extend through at least a subset of the IMD layers; and a through silicon via (TSV) structure extending through the semiconductor substrate and the subset of IMD layers to electrically contact one of the metal features. The first guard ring surrounds the TSV structure; and the second guard ring surrounds the first guard ring and is configured to reduce a parasitic capacitance between the guard ring structure and the TSV structure.

2. 发明授权

US11855130B2 Three-dimensional device structure including substrate-embedded integrated passive device and methods for making the same 有权
公开(公告)号：US11855130B2
公开(公告)日：2023-12-26
申请号：US17446053
申请日：2021-08-26
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Jen-Yuan Chang , Chien-Chang Lee , Chia-Ping Lai , Tzu-Chung Tsai
IPC分类号： H01L21/00 , H01L49/02 , H01L23/48 , H01L25/065 , H01L23/00 , H01L23/498
CPC分类号： H01L28/90 , H01L23/481 , H01L23/49816 , H01L24/08 , H01L24/32 , H01L24/33 , H01L25/0657 , H01L2224/08146 , H01L2224/09181 , H01L2224/32145 , H01L2224/33181 , H01L2225/06541
摘要： A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.

3. 发明授权

US12040242B2 Three-dimensional device structure including seal ring connection circuit 有权
公开(公告)号：US12040242B2
公开(公告)日：2024-07-16
申请号：US17412469
申请日：2021-08-26
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Jen-Yuan Chang , Chien-Chang Lee , Chia-Ping Lai
IPC分类号： H01L23/552 , H01L23/10 , H01L23/522 , H01L23/535 , H01L23/538 , H01L23/60 , H01L27/06
CPC分类号： H01L23/10 , H01L23/5226 , H01L23/535 , H01L23/5383 , H01L23/60 , H01L27/0688 , H01L23/5225
摘要： A three-dimensional device structure includes a first die, a second die disposed on the first die, and a connection circuit. The first die includes a first semiconductor substrate, a first interconnect structure disposed on the first semiconductor substrate, and a first seal ring surrounding the interconnect structure. The second die includes a second semiconductor substrate, a second interconnect structure disposed on the second semiconductor substrate, and a second seal ring surrounding the interconnect structure. The first connection circuit electrically couples the first seal ring to the second seal ring to provide an electrostatic discharge path.

4. 发明授权

US12009405B2 Deep trench capacitor including a compact contact region and methods of forming the same 有权
公开(公告)号：US12009405B2
公开(公告)日：2024-06-11
申请号：US17460178
申请日：2021-08-28
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Jen-Yuan Chang , Chia-Ping Lai , Chien-Chang Lee
IPC分类号： H01L29/66 , H01G2/02 , H01G7/02
CPC分类号： H01L29/66181 , H01G2/02 , H01G7/021
摘要： A deep trench capacitor includes at least one deep trench and a layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers and continuously extending over the top surface of a substrate and into each of the at least one deep trench. A contact-level dielectric layer overlies the substrate and the layer stack. Contact assemblies extend through the contact-level dielectric layer. A subset of the contact assemblies vertically extend through a respective metallic electrode layer. For example, a first contact assembly includes a first tubular insulating spacer that laterally surrounds a first contact via structure and contacts a cylindrical sidewall of a topmost metallic electrode layer.

5. 发明授权

US11908838B2 Three-dimensional device structure including embedded integrated passive device and methods of making the same 有权
公开(公告)号：US11908838B2
公开(公告)日：2024-02-20
申请号：US17446038
申请日：2021-08-26
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Jen-Yuan Chang , Chien-Chang Lee , Chia-Ping Lai , Tzu-Chung Tsai
IPC分类号： H01L49/02 , H01L25/065 , H01L25/00 , H01L21/56 , H01L23/00 , H01L23/31
CPC分类号： H01L25/0657 , H01L21/56 , H01L25/50 , H01L28/60 , H01L23/3121 , H01L23/3157 , H01L24/08 , H01L24/32 , H01L2224/08145 , H01L2224/32145 , H01L2225/06524 , H01L2225/06548 , H01L2225/06568
摘要： A three-dimensional device structure includes a first die including a first semiconductor substrate, a second die disposed on the first die and including a second semiconductor substrate, a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die, a redistribution layer structure disposed on the second die and the DE layer, and an integrated passive device (IPD) embedded in the DE layer and electrically connected to the first die and the redistribution layer structure.

6. 发明授权

US11728288B2 Semiconductor die including guard ring structure and three-dimensional device structure including the same 有权
公开(公告)号：US11728288B2
公开(公告)日：2023-08-15
申请号：US17458687
申请日：2021-08-27
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Jen-Yuan Chang , Chien-Chang Lee , Chia-Ping Lai
IPC分类号： H01L21/00 , H01L23/58 , H01L23/48 , H01L23/522 , H01L21/768 , H01L25/065 , H01L25/18 , H01L23/00
CPC分类号： H01L23/585 , H01L21/76898 , H01L23/481 , H01L23/5222 , H01L25/0657 , H01L23/562 , H01L25/18 , H01L2225/06544
摘要： A die includes: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate and including: inter-metal dielectric (IMD) layers; metal features embedded in the IMD layers; and a guard ring structure including concentric first and second guard rings that extend through at least a subset of the IMD layers; and a through silicon via (TSV) structure extending through the semiconductor substrate and the subset of IMD layers to electrically contact one of the metal features. The first guard ring surrounds the TSV structure; and the second guard ring surrounds the first guard ring and is configured to reduce a parasitic capacitance between the guard ring structure and the TSV structure.

7. 发明授权

US11442230B2 Silicon photonics coupling structure using an etch stop layer and methods of forming the same 有权
公开(公告)号：US11442230B2
公开(公告)日：2022-09-13
申请号：US17097197
申请日：2020-11-13
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Yueh Ying Lee , Chien-Ying Wu , Sui-Ying Hsu , Chen-Hao Huang , Chien-Chang Lee , Chia-Ping Lai
IPC分类号： G02B6/34
摘要： An optical structure may be provided by forming a silicon grating structure over a dielectric material layer, depositing at least one dielectric material layer over the silicon grating structure, and depositing at least one dielectric etch stop layer over the at least one dielectric material layer. The at least one dielectric etch stop layer includes at least one dielectric material selected from silicon nitride and silicon oxynitride. A passivation dielectric layer may be formed over the at least one dielectric etch stop layer, and a patterned etch mask layer may be formed over the passivation dielectric layer. An opening may be formed through an unmasked portion of the passivation dielectric layer by performing an anisotropic etch process that etches the dielectric material selective to a silicon nitride or silicon oxynitride using the patterned etch mask layer as a masking structure. The at least one etch mask layer minimizes overetching.

8. 发明申请

US20150268271A1 MULTIDIRECTIONAL SEMICONDUCTOR ARRANGEMENT TESTING 有权
标题翻译：多功能半导体器件布置测试
公开(公告)号：US20150268271A1
公开(公告)日：2015-09-24
申请号：US14221543
申请日：2014-03-21
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Tseng-Chin Lo , Huan Chi Tseng , Kuo-Chuan Chang , Yuan-Yao Chang , Chien-Chang Lee
IPC分类号： G01R1/04 , G01R31/26
CPC分类号： G01R1/0491 , G01R1/07364 , G01R31/2601
摘要： One or more probe cards, wafer testers, and techniques for testing a semiconductor arrangement are provided. Testline arrangements are formed within scribe lines of a semiconductor wafer, in multiple directions, such as an x-direction and a y-direction. A wafer tester is configured to concurrently test the semiconductor arrangement in multiple directions using a multidirectional probe arrangement of a probe card. In some embodiments, a first pin arrangement of the multidirectional probe arrangement is mated with a first testline arrangement in a first direction, and a second pin arrangement of the multidirectional probe arrangement is mated with a second testline arrangement in a second direction. The wafer tester concurrently tests the semiconductor arrangement in multiple directions, such as in the first direction and the second direction, through the pin arrangements mated with the testline arrangements.
摘要翻译：提供了一个或多个探针卡，晶片测试器和用于测试半导体布置的技术。测试线布置在诸如x方向和y方向的多个方向上形成在半导体晶片的划线内。晶片测试器被配置为使用探针卡的多向探针布置来同时测试多个方向上的半导体布置。在一些实施例中，多向探针装置的第一引脚装置与第一测试线布置在第一方向配合，并且多向探针装置的第二引脚布置与第二测试线布置在第二方向配合。晶片测试器通过与测试线布置配合的引脚布置，同时在多个方向（例如沿第一方向和第二方向）测试半导体布置。

9. 发明申请

US20230060265A1 THREE-DIMENSIONAL INTEGRATED CIRCUIT 有权
公开(公告)号：US20230060265A1
公开(公告)日：2023-03-02
申请号：US17460181
申请日：2021-08-28
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Jen-Yuan Chang , Chia-Ping Lai , Chien-Chang Lee
IPC分类号： H01L25/065 , H01L23/538
摘要： A die stack includes: a first die including a first semiconductor substrate; a first redistribution layer (RDL) structure disposed on a front surface of the first die and electrically connected to the first semiconductor substrate; a second die bonded to the front surface of the first die and including a second semiconductor substrate; a third die bonded to the front surface of the first die and including a third semiconductor substrate; a second RDL structure disposed on front surfaces of the second and third dies and electrically connected to the second and third semiconductor substrates; and a through dielectric via (TDV) structure extending between the second and third dies and electrically connected to the first RDL structure and second RDL structure. The second and third dies are disposed in a plane that extends perpendicular to a vertical stacking direction of the die stack.

10. 发明申请

US20230069774A1 DEEP TRENCH CAPACITOR INCLUDING A COMPACT CONTACT REGION AND METHODS OF FORMING THE SAME 有权
公开(公告)号：US20230069774A1
公开(公告)日：2023-03-02
申请号：US17460178
申请日：2021-08-28
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Jen-Yuan CHANG , Chia-Ping Lai , Chien-Chang Lee
IPC分类号： H01L29/66 , H01G7/02 , H01G2/02
摘要： A deep trench capacitor includes at least one deep trench and a layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers and continuously extending over the top surface of a substrate and into each of the at least one deep trench. A contact-level dielectric layer overlies the substrate and the layer stack. Contact assemblies extend through the contact-level dielectric layer. A subset of the contact assemblies vertically extend through a respective metallic electrode layer. For example, a first contact assembly includes a first tubular insulating spacer that laterally surrounds a first contact via structure and contacts a cylindrical sidewall of a topmost metallic electrode layer.

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