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1. 发明申请

US20140232000A1 SEMICONDUCTOR ARRANGEMENT AND FORMATIN THEREOF 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20140232000A1
公开(公告)日：2014-08-21
申请号：US14265437
申请日：2014-04-30
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Chien-Hua Huang , Hsin-Chieh Yao , Chung-Ju Lee
IPC分类号： H01L21/768 , H01L23/532 , H01L23/522
CPC分类号： H01L21/7682 , H01L21/76804 , H01L21/76885 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes conductive lines having sidewalls angled between about 45° to about 90° relative to a plane in which bottom surfaces of the conductive lines lie. A dielectric layer is formed over the conductive lines, where forming the dielectric layer after the conductive lines are formed mitigates damage to the dielectric layer, such as by not subjecting the dielectric layer to etching. The angled sidewalls of the conductive lines cause the dielectric layer to pinch off before an area between adjacent conductive lines is filled, thus establishing an air gap between adjacent conductive lines, where the air gap has a lower dielectric constant than the dielectric material. At least one of the substantially undamaged dielectric layer or the air gap serves to reduce parasitic capacitance within the semiconductor arrangement, which improves performance.
摘要翻译：提供了半导体布置和形成方法。半导体装置包括具有相对于导线的底表面所在的平面在约45°至约90°之间成角度的侧壁的导电线。在导电线上形成电介质层，其中在形成导电线之后形成电介质层，例如通过不对电介质层进行蚀刻来减轻电介质层的损伤。导电线的成角度的侧壁使得介电层在相邻导线之间的区域被填充之前被夹紧，从而在相邻导电线之间形成气隙，其中气隙具有比介电材料低的介电常数。基本上未损坏的介电层或气隙中的至少一个用于减小半导体布置内的寄生电容，这提高了性能。

2. 发明授权

US11569127B2 Double patterning approach by direct metal etch 有权
公开(公告)号：US11569127B2
公开(公告)日：2023-01-31
申请号：US17192573
申请日：2021-03-04
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Hsi-Wen Tien , Wei-Hao Liao , Yu-Teng Dai , Hsin-Chieh Yao , Chih-Wei Lu , Chung-Ju Lee
IPC分类号： H01L21/768 , H01L21/3213
摘要： In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance.

3. 发明申请

US20220285214A1 THE NOVEL DOUBLE PATTERNING APPROACH BY DIRECT METAL ETCH 有权
公开(公告)号：US20220285214A1
公开(公告)日：2022-09-08
申请号：US17192573
申请日：2021-03-04
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： HSI-WEN TIEN , Wei-Hao Liao , Yu-Teng Dai , Hsin-Chieh Yao , Chih-Wei Lu , Chung-Ju Lee
IPC分类号： H01L21/768 , H01L21/3213
摘要： In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance.

4. 发明授权

US09490163B2 Tapered sidewall conductive lines and formation thereof 有权
标题翻译：锥形侧壁导电线及其形成
公开(公告)号：US09490163B2
公开(公告)日：2016-11-08
申请号：US14265437
申请日：2014-04-30
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Chien-Hua Huang , Hsin-Chieh Yao , Chung-Ju Lee
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/7682 , H01L21/76804 , H01L21/76885 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes conductive lines having sidewalls angled between about 45° to about 90° relative to a plane in which bottom surfaces of the conductive lines lie. A dielectric layer is formed over the conductive lines. The angled sidewalls of the conductive lines cause the dielectric layer to pinch off before an area between adjacent conductive lines is filled, thus establishing an air gap between adjacent conductive lines, where the air gap has a lower dielectric constant than the dielectric material.
摘要翻译：提供了半导体布置和形成方法。半导体装置包括具有相对于导线的底表面所在的平面在约45°至约90°之间成角度的侧壁的导电线。在导电线上形成电介质层。导电线的成角度的侧壁使得介电层在相邻导线之间的区域被填充之前被夹紧，从而在相邻导电线之间形成气隙，其中气隙具有比介电材料低的介电常数。

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