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1. 发明申请

US20210336613A1 SYSTEM AND METHOD FOR ADJUSTING CYCLE OF A SIGNAL 有权
公开(公告)号：US20210336613A1
公开(公告)日：2021-10-28
申请号：US17178899
申请日：2021-02-18
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Ruey-Bin Sheen , Ming Hsien Tsai , Tsung-Hsien Tsai
IPC分类号： H03K5/156 , H03K5/06 , H03K3/017 , G04F10/00
摘要： A duty cycle adjustment system includes a time-to-digital converter to generate a plurality of time-to-digital codes from an input signal, a duty cycle index generator to compute a duty cycle of the input signal based upon the plurality of time-to-digital codes, and assign a duty cycle index based upon the computed duty cycle, an input phase assignment generator to generate a first output and a second output based upon the duty cycle index, a first delay line to delay the first output to generate a third output, and a duty cycle generator to adjust the duty cycle of the input signal based upon the third output and the second output.

2. 发明授权

US09219471B2 Circuitry for phase detector 有权
标题翻译：相位检测器电路
公开(公告)号：US09219471B2
公开(公告)日：2015-12-22
申请号：US14260315
申请日：2014-04-24
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Tsung-Hsien Tsai , Chia-Chun Liao
IPC分类号： H03D13/00 , H03K5/14 , H03K3/356
CPC分类号： H03K5/14 , H03D13/009 , H03K5/15066 , H03K5/1508
摘要： A circuit for a phase detector is provided. A first buffer of the circuit receives a data signal and generates a first modified data signal using the data signal. A notifier receives the data signal and determines whether a violation exists. A first multiplexer receives the first modified data signal and transmits a first multiplexer signal to a second multiplexer. The second multiplexer receives the first multiplexer data signal and the first modified data signal, and transmits a second multiplexer data signal to a flip-flop of the phase detector.
摘要翻译：提供了一种用于相位检测器的电路。电路的第一缓冲器接收数据信号并使用数据信号产生第一修改数据信号。通知器接收数据信号并确定是否存在违规。第一多路复用器接收第一修改数据信号并将第一多路复用器信号发送到第二多路复用器。第二多路复用器接收第一多路复用器数据信号和第一修改数据信号，并将第二多路复用器数据信号发送到相位检测器的触发器。

3. 发明申请

US20210226584A1 Oscillator Circuits and Methods for Realignment of an Oscillator Circuit 有权
公开(公告)号：US20210226584A1
公开(公告)日：2021-07-22
申请号：US17120378
申请日：2020-12-14
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Tsung-Hsien Tsai , Ruey-Bin Sheen , Chih-Hsien Chang , Cheng-Hsiang Hsieh
IPC分类号： H03B5/12 , H03B5/04 , H03L7/081 , H03K3/00 , H03B17/00 , H03L7/26 , H03K5/156
摘要： Oscillators and methods for realignment of an oscillator are provided. An oscillator includes an inductor having first and second terminals and a capacitor electrically coupled in parallel to the inductor at the first and second terminals. A first transistor of a first conductivity type is electrically coupled to the first terminal and a voltage source. The first transistor includes a gate configured to receive a first realignment signal. When the first realignment signal is in a realignment state, the first transistor is turned on and a voltage of the first terminal is increased from a low level to a high level in order to align a phase of a waveform of the oscillator.

4. 发明授权

US10958257B1 System and method for adjusting duty cycle of a signal 有权
公开(公告)号：US10958257B1
公开(公告)日：2021-03-23
申请号：US16860568
申请日：2020-04-28
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Ruey-Bin Sheen , Ming Hsien Tsai , Tsung-Hsien Tsai
IPC分类号： H03K5/04 , H03K5/156 , G04F10/00 , H03K3/017 , H03K5/06
摘要： A duty cycle adjustment system includes a time-to-digital converter to generate a plurality of time-to-digital codes from an input signal, a duty cycle index generator to compute a duty cycle of the input signal based upon the plurality of time-to-digital codes, and assign a duty cycle index based upon the computed duty cycle, an input phase assignment generator to generate a first output and a second output based upon the duty cycle index, a first delay line to delay the first output to generate a third output, and a duty cycle generator to adjust the duty cycle of the input signal based upon the third output and the second output.

5. 发明授权

US09379718B2 All-digital phase-locked loop (ADPLL) 有权
标题翻译：全数字锁相环（ADPLL）
公开(公告)号：US09379718B2
公开(公告)日：2016-06-28
申请号：US14261467
申请日：2014-04-25
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Tsung-Hsien Tsai
IPC分类号： H03L7/08
CPC分类号： H03L7/0802 , H03L2207/50
摘要： An all-digital phase-locked loop (ADPLL) is provided. The ADPLL comprises a first circuit and a second circuit. The first circuit is configured to monitor a first signal and set a voltage of a second signal to a voltage within a first voltage range when a code of fine-tuning is equal to a first specified value. The first circuit is configured to set a voltage of a third signal to a voltage within a second voltage range when the code of fine-tuning is equal to a second specified value. The second circuit is configured to increase a code of coarse-tuning when the voltage of the second signal is within the first voltage range, and decrease the code of coarse-tuning when the voltage of the third signal is within the second voltage range. The ADPLL provides a target frequency despite changes in at least one of process, voltage or temperature.
摘要翻译：提供全数字锁相环（ADPLL）。 ADPLL包括第一电路和第二电路。第一电路被配置为当微调代码等于第一指定值时，监视第一信号并将第二信号的电压设置为第一电压范围内的电压。第一电路被配置为当微调代码等于第二指定值时，将第三信号的电压设置为第二电压范围内的电压。第二电路被配置为当第二信号的电压处于第一电压范围内时增加粗调编码，并且当第三信号的电压处于第二电压范围内时，减小粗调码。尽管在过程，电压或温度中的至少一个有变化，ADPLL提供了目标频率。

6. 发明申请

US20150311905A1 ALL-DIGITAL PHASE-LOCKED LOOP (ADPLL) 有权
标题翻译：全数字锁相环（ADPLL）
公开(公告)号：US20150311905A1
公开(公告)日：2015-10-29
申请号：US14261467
申请日：2014-04-25
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Tsung-Hsien Tsai
IPC分类号： H03L7/08
CPC分类号： H03L7/0802 , H03L2207/50
摘要： An all-digital phase-locked loop (ADPLL) is provided. The ADPLL comprises a first circuit and a second circuit. The first circuit is configured to monitor a first signal and set a voltage of a second signal to a voltage within a first voltage range when a code of fine-tuning is equal to a first specified value. The first circuit is configured to set a voltage of a third signal to a voltage within a second voltage range when the code of fine-tuning is equal to a second specified value. The second circuit is configured to increase a code of coarse-tuning when the voltage of the second signal is within the first voltage range, and decrease the code of coarse-tuning when the voltage of the third signal is within the second voltage range. The ADPLL provides a target frequency despite changes in at least one of process, voltage or temperature.
摘要翻译：提供全数字锁相环（ADPLL）。 ADPLL包括第一电路和第二电路。第一电路被配置为当微调代码等于第一指定值时，监视第一信号并将第二信号的电压设置为第一电压范围内的电压。第一电路被配置为当微调代码等于第二指定值时，将第三信号的电压设置为第二电压范围内的电压。第二电路被配置为当第二信号的电压处于第一电压范围内时增加粗调编码，并且当第三信号的电压处于第二电压范围内时，减小粗调码。尽管在过程，电压或温度中的至少一个有变化，ADPLL提供了目标频率。

7. 发明授权

US11031927B2 Systems and methods for generating a controllable-width pulse signal 有权
公开(公告)号：US11031927B2
公开(公告)日：2021-06-08
申请号：US16733379
申请日：2020-01-03
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Ruey-Bin Sheen , Ming Hsien Tsai , Chih-Hsien Chang , Tsung-Hsien Tsai
IPC分类号： H03K5/14 , H03K5/131 , H03K5/135 , G04F10/00 , H03K5/00
摘要： Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.

8. 发明授权

US11539355B2 Systems and methods for generating a controllable-width pulse signal 有权
公开(公告)号：US11539355B2
公开(公告)日：2022-12-27
申请号：US17313091
申请日：2021-05-06
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Ruey-Bin Sheen , Ming Hsien Tsai , Chih-Hsien Chang , Tsung-Hsien Tsai
IPC分类号： H03K5/14 , H03K5/131 , H03K5/135 , G04F10/00 , H03K5/00
摘要： Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.

9. 发明授权

US11539354B2 Systems and methods for generating a controllable-width pulse signal 有权
公开(公告)号：US11539354B2
公开(公告)日：2022-12-27
申请号：US17233735
申请日：2021-04-19
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Ruey-Bin Sheen , Ming Hsien Tsai , Chih-Hsien Chang , Tsung-Hsien Tsai
IPC分类号： H03K5/14 , H03K5/131 , H03K5/135 , G04F10/00 , H03K5/00
摘要： Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.

10. 发明授权

US11290096B2 System and method for adjusting cycle of a signal 有权
公开(公告)号：US11290096B2
公开(公告)日：2022-03-29
申请号：US17178899
申请日：2021-02-18
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Ruey-Bin Sheen , Ming Hsien Tsai , Tsung-Hsien Tsai
IPC分类号： H03K5/156 , G04F10/00 , H03K3/017 , H03K5/06
摘要： A duty cycle adjustment system includes a time-to-digital converter to generate a plurality of time-to-digital codes from an input signal, a duty cycle index generator to compute a duty cycle of the input signal based upon the plurality of time-to-digital codes, and assign a duty cycle index based upon the computed duty cycle, an input phase assignment generator to generate a first output and a second output based upon the duty cycle index, a first delay line to delay the first output to generate a third output, and a duty cycle generator to adjust the duty cycle of the input signal based upon the third output and the second output.

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