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1. 发明授权

US08947953B2 Bit cell internal voltage control 有权
标题翻译：位单元内部电压控制
公开(公告)号：US08947953B2
公开(公告)日：2015-02-03
申请号：US13731084
申请日：2012-12-30
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Wei Min Chan , Yi-Tzu Chen , Wei-Cheng Wu , Yen-Huei Chen , Hau-Tai Shieh
IPC分类号： G11C7/10 , G11C5/14 , G11C7/22 , G11C11/419
CPC分类号： G11C5/147 , G11C7/10 , G11C7/22 , G11C7/227 , G11C11/419
摘要： Among other things, techniques for facilitating a write operation to a bit cell are provided. A pulse generator initializes lowering of an internal voltage level associated with a bit cell that is to be written to by a write operation. In this way, the bit cell is placed into a writeable voltage state, such that a potential of the bit cell can be overcome by the write operation. A voltage detector sends a reset signal to the pulse generator based upon the pulse generator lowering the internal voltage level past a reset trigger level. Responsive to receiving the reset signal, the pulse generator initializes charging of the internal voltage level to an original voltage level. In this way, the lowering of the internal voltage level is controlled so that one or more other bit cells are not affected (e.g., suffer data retention failure) by the relatively lower internal voltage level.
摘要翻译：其中，提供了用于促进对位单元的写操作的技术。脉冲发生器初始化与由写入操作写入的位单元相关联的内部电压电平的降低。以这种方式，位单元被置于可写入电压状态，使得可以通过写入操作来克服位单元的电位。电压检测器基于脉冲发生器将内部电压电平降低到复位触发电平来向脉冲发生器发送复位信号。响应于接收复位信号，脉冲发生器将内部电压电平的充电初始化为原始电压电平。以这种方式，控制内部电压电平的降低，使得一个或多个其它位单元不受相对较低的内部电压电平的影响（例如，遭受数据保持故障）。

2. 发明申请

US20210383847A1 Multi-Stage Bit Line Pre-Charge 有权
公开(公告)号：US20210383847A1
公开(公告)日：2021-12-09
申请号：US17408567
申请日：2021-08-23
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Wei-Cheng Wu , Kao-Cheng Lin , Chih-Cheng Yu , Pei-Yuan Li , Chien-Chen Lin , Wei Min Chan , Yen-Huei Chen
IPC分类号： G11C7/12 , G11C11/419 , G11C7/10 , G11C11/4093 , G11C11/4091 , G11C11/4094 , G11C11/4076 , G11C11/416 , G11C11/413 , G11C11/4096
摘要： Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

3. 发明申请

US20210249057A1 Multi-Stage Bit Line Pre-Charge 有权
公开(公告)号：US20210249057A1
公开(公告)日：2021-08-12
申请号：US16785875
申请日：2020-02-10
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Wei-Cheng Wu , Kao-Cheng Lin , Chih-Cheng Yu , Pei-Yuan Li , Chien-Chen Lin , Wei Min Chan , Yen-Huei Chen
IPC分类号： G11C7/12 , G11C7/10 , G11C11/419
摘要： Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

4. 发明授权

US09685223B2 Voltage controller 有权
公开(公告)号：US09685223B2
公开(公告)日：2017-06-20
申请号：US14079825
申请日：2013-11-14
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Wei-Cheng Wu , Wei Min Chan , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： G11C11/417 , G11C11/419
CPC分类号： G11C11/417 , G11C11/419
摘要： A voltage controller is provided that is connected to a voltage inducing circuit which is connected to a static random-access memory (SRAM) cell. The voltage controller comprises a voltage clamping circuit and a pull up circuit. The voltage clamping circuit comprises one or more transistors. The voltage clamping circuit is configured to inhibit a second voltage of a second signal at a second node of the voltage inducing circuit from exceeding a first specified voltage threshold so that a fifth voltage of a fifth signal at a fifth node of the voltage inducing circuit is inhibited from exceeding a second specified voltage threshold. The pull up circuit is configured to maintain the second voltage substantially equal to a specified pull up voltage. The fifth node is connected to the SRAM cell, and a voltage to which the SRAM cell is exposed is thereby controlled.

5. 发明申请

US20150131366A1 VOLTAGE CONTROLLER 有权
标题翻译：电压控制器
公开(公告)号：US20150131366A1
公开(公告)日：2015-05-14
申请号：US14079825
申请日：2013-11-14
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Wei-Cheng Wu , Wei Min Chan , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： G11C11/417
CPC分类号： G11C11/417 , G11C11/419
摘要： A voltage controller is provided that is connected to a voltage inducing circuit which is connected to a static random-access memory (SRAM) cell. The voltage controller comprises a voltage clamping circuit and a pull up circuit. The voltage clamping circuit comprises one or more transistors. The voltage clamping circuit is configured to inhibit a second voltage of a second signal at a second node of the voltage inducing circuit from exceeding a first specified voltage threshold so that a fifth voltage of a fifth signal at a fifth node of the voltage inducing circuit is inhibited from exceeding a second specified voltage threshold. The pull up circuit is configured to maintain the second voltage substantially equal to a specified pull up voltage. The fifth node is connected to the SRAM cell, and a voltage to which the SRAM cell is exposed is thereby controlled.
摘要翻译：提供一个电压控制器，其连接到连接到静态随机存取存储器（SRAM）单元的电压感应电路。电压控制器包括钳位电路和上拉电路。钳位电路包括一个或多个晶体管。电压钳位电路被配置为在电压感应电路的第二节点处禁止第二信号的第二电压超过第一指定电压阈值，使得电压感应电路的第五节点处的第五信号的第五电压为禁止超过第二规定电压阈值。上拉电路被配置为保持第二电压基本上等于指定的上拉电压。第五节点连接到SRAM单元，由此控制SRAM单元暴露于的电压。

6. 发明授权

US11100964B1 Multi-stage bit line pre-charge 有权
公开(公告)号：US11100964B1
公开(公告)日：2021-08-24
申请号：US16785875
申请日：2020-02-10
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Wei-Cheng Wu , Kao-Cheng Lin , Chih-Cheng Yu , Pei-Yuan Li , Chien-Chen Lin , Wei Min Chan , Yen-Huei Chen
IPC分类号： G11C7/12 , G11C11/419 , G11C7/10 , G11C11/4093 , G11C11/4091 , G11C11/4094 , G11C11/4076 , G11C11/416 , G11C11/413 , G11C11/4096
摘要： Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

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