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    • 5. 发明申请
    • PROTECTIVE RELAYING DEVICE
    • 保护继电器
    • US20130090875A1
    • 2013-04-11
    • US13687019
    • 2012-11-28
    • Atsushi TAKEUCHI
    • Atsushi TAKEUCHI
    • G01R17/12
    • G01R17/12H02H3/302H03L7/00H04J3/00
    • According to one embodiment, a protective relaying device includes a phase difference calculating unit configured to calculate a phase difference between a phase obtained by shifting a phase of first current data by 180°, and a phase of second current data, a setting unit configured to calculate a target value of elimination of a sampling synchronization error caused by a difference between a transmission delay time of up-transmission, and a transmission delay time of down-transmission on the basis of the phase difference, and to set the calculated target value, and a sampling synchronization control unit configured to carry out control of sampling synchronization such that a difference between a time TM and a time TF.
    • 根据一个实施例,保护中继装置包括:相位差计算单元,被配置为计算通过将第一电流数据的相位移位180°而获得的相位与第二电流数据的相位之间的相位差;设置单元, 根据相位差计算由上传传输延迟时间和下传传输延迟时间之间的差引起的取样同步误差消除的目标值,并设定计算出的目标值, 以及采样同步控制单元,被配置为执行采样同步的控制,使得时间TM和时间TF之间的差异。
    • 8. 发明申请
    • Internal Power Supply Circuit Having a Cascode Current Mirror Circuit
    • 具有串联电流镜电路的内部电源电路
    • US20090230770A1
    • 2009-09-17
    • US12147098
    • 2008-06-26
    • Atsushi TAKEUCHIAtsumasa Sako
    • Atsushi TAKEUCHIAtsumasa Sako
    • G05F3/08
    • G11C11/4074G11C5/143G11C5/147Y10T307/50Y10T307/76
    • A current mirror circuit which is connected to first and second power supplies and generates a desired current, has a plurality of first transistors which are connected in parallel to the first power supply side and the gates of which are connected to a common node, a plurality of second transistors which are cascode-connected to the plurality of first transistors and the gates of which are supplied with a cascode bias potential and a cascode bias generation circuit which generates the cascode bias potential, wherein the cascode bias generation circuit maintains the cascode bias potential during normal operation at a first potential between the potentials of the first and second power supplies, and maintains the cascode bias potential during power-on at a second potential closer to the potential of the second power supply than the first potential.
    • 连接到第一和第二电源并产生期望电流的电流镜电路具有并联连接到第一电源侧并且其栅极连接到公共节点的多个第一晶体管,多个 第二晶体管被共模连接到多个第一晶体管并且其栅极被提供有共源共栅偏压电位和产生共源共栅偏压电位的共源共栅偏压产生电路,其中共源共栅偏压产生电路保持共源共栅偏压电位 在第一和第二电源的电位之间的第一电势的正常操作期间,并且在第二电位处的上电期间保持级联偏置电位,该第二电位比第一电位更接近第二电源的电位。