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1. 发明申请

US20190341773A1 ESD Protection Charge Pump Active Clamp for Low-Leakage Applications 审中-公开
公开(公告)号：US20190341773A1
公开(公告)日：2019-11-07
申请号：US16511332
申请日：2019-07-15
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： James P. Di Sarro , Farzan Farbiz
IPC分类号： H02H9/04 , H02H1/00 , H01L27/02
摘要： Disclosed examples include an electrostatic discharge protection circuit including a shunt transistor coupled between first and second power supply nodes, a sensing circuit to deliver a control voltage signal to turn on the shunt transistor in response to a detected change in a voltage of the first power supply node resulting from an ESD stress event, and a charge pump circuit to boost the control voltage signal in response to the control voltage signal turning the shunt transistor on.

2. 发明授权

US10396199B2 Electrostatic discharge device 有权
公开(公告)号：US10396199B2
公开(公告)日：2019-08-27
申请号：US15624741
申请日：2017-06-16
申请人： Texas Instruments Incorporated
发明人： Aravind C. Appaswamy , Akram A. Salman , Farzan Farbiz , Gianluca Boselli
IPC分类号： H02H9/00 , H01L29/78 , H01L27/02 , H01L29/10
摘要： A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.

3. 发明授权

US10181721B2 Area-efficient active-FET ESD protection circuit 有权
公开(公告)号：US10181721B2
公开(公告)日：2019-01-15
申请号：US15434280
申请日：2017-02-16
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Xianzhi Dai , Farzan Farbiz , Muhammad Yusuf Ali
IPC分类号： H02H9/04 , H01L23/528 , H01L27/02 , H01L27/06 , H01L27/092
摘要： An electrostatic discharge (ESD) protection circuit includes a high power supply rail (VDD) and a low power supply rail (VSS). The ESD protection circuit further includes an active shunt transistor coupled between VDD and VSS. The active shunt transistor includes a gate. The ESD protection circuit also includes a sensing transistor connected between an input/output (I/O) pad and the gate of the active shunt transistor. If an ESD stress event occurs on the I/O pad or on a VDD pad, the sensing transistor is caused to be turned ON thereby permitting a voltage on the I/O or VDD pad experiencing the ESD stress event to turn ON the active shunt transistor in turn causing ESD current to flow from the pad experiencing the ESD event, through VDD, and through the active shunt transistor to VSS.

4. 发明授权

US09818868B2 Metal oxide semiconductor and method of making 有权
公开(公告)号：US09818868B2
公开(公告)日：2017-11-14
申请号：US14543123
申请日：2014-11-17
申请人： Texas Instruments Incorporated
发明人： Aravind C. Appaswamy , Akram A. Salman , Farzan Farbiz
IPC分类号： H01L29/78 , H01L29/66 , H01L29/45 , H01L29/06 , H01L27/02
CPC分类号： H01L29/7835 , H01L27/027 , H01L29/0696 , H01L29/456 , H01L29/66659
摘要： A drain extended metal oxide semiconductor (MOS) includes a substrate having a semiconductor. A gate is located on the semiconductor, a source is located on the semiconductor and on one side of the gate, and a drain is located on the semiconductor and on another side of said gate. The MOS includes least one first finger having a first finger drain component located adjacent the drain, the first finger drain component has a silicide layer. At least one second finger has a second finger drain component located adjacent the drain, the second finger drain component has less silicide than the first finger drain component.

5. 发明授权

US09633991B2 Mutual ballasting multi-finger bidirectional ESD device 有权
公开(公告)号：US09633991B2
公开(公告)日：2017-04-25
申请号：US14949417
申请日：2015-11-23
申请人： Texas Instruments Incorporated
发明人： Akram A. Salman , Farzan Farbiz , Ann Margaret Concannon , Gianluca Boselli
IPC分类号： H01L27/02 , H02H9/04
CPC分类号： H01L27/0262 , H01L27/0248 , H01L27/0259 , H01L27/0266 , H02H9/046
摘要： An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.

6. 发明申请

US20150294967A1 ESD PROTECTION CIRCUIT WITH ISOLATED SCR FOR NEGATIVE VOLTAGE OPERATION 审中-公开
标题翻译：具有隔离SCR的ESD保护电路用于负压运行
公开(公告)号：US20150294967A1
公开(公告)日：2015-10-15
申请号：US14750339
申请日：2015-06-25
申请人： Texas Instruments Incorporated
发明人： Akram A. Salman , Farzan Farbiz , Amitava Chatterjee , Xiaoju Wu
IPC分类号： H01L27/02 , H01L29/10 , H01L29/74
CPC分类号： H01L27/0262 , H01L29/1012 , H01L29/7424 , H01L29/7436
摘要： A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.
摘要翻译：公开了一种用于集成电路的半导体可控整流器（图4A）。半导体可控整流器包括具有第一导电类型（N）的第一轻掺杂区域（100）和在第一轻掺杂区域内形成的具有第二导电类型（P）的第一重掺杂区域（108）。具有第二导电类型的第二轻掺杂区域（104）形成在第一轻掺杂区域附近。在第二轻掺杂区域内形成具有第一导电类型的第二重掺杂区域（114）。具有第一导电类型的掩埋层（101）形成在第二轻掺杂区域的下方并且电连接到第一轻掺杂区域。在第二轻掺杂区域和第三重掺杂区域之间形成具有第二导电类型的第三轻掺杂区域（102）。具有第二导电类型的第四轻掺杂区域（400）形成在第二轻掺杂区域和第三重掺杂区域之间，并且电连接到第二和第三轻掺杂区域。

7. 发明申请

US20220189946A1 ESD PROTECTION CIRCUIT WITH ISOLATED SCR FOR NEGATIVE VOLTAGE OPERATION 有权
公开(公告)号：US20220189946A1
公开(公告)日：2022-06-16
申请号：US17687380
申请日：2022-03-04
申请人： Texas Instruments Incorporated
发明人： Akram A. Salman , Farzan Farbiz , Amitava Chatterjee , Xiaoju Wu
IPC分类号： H01L27/02 , H01L29/74 , H01L29/10
摘要： A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

8. 发明授权

US11302688B2 ESD protection circuit with isolated SCR for negative voltage operation 有权
公开(公告)号：US11302688B2
公开(公告)日：2022-04-12
申请号：US16054037
申请日：2018-08-03
申请人： Texas Instruments Incorporated
发明人： Akram A. Salman , Farzan Farbiz , Amitava Chatterjee , Xiaoju Wu
IPC分类号： H01L27/02 , H01L29/73 , H01L29/74 , H01L29/10
摘要： A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

9. 发明授权

US11049852B2 ESD protection circuit with isolated SCR for negative voltage operation 有权
公开(公告)号：US11049852B2
公开(公告)日：2021-06-29
申请号：US16053985
申请日：2018-08-03
申请人： Texas Instruments Incorporated
发明人： Akram A. Salman , Farzan Farbiz , Amitava Chatterjee , Xiaoju Wu
IPC分类号： H01L27/02 , H01L29/10 , H01L29/74
摘要： A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

10. 发明授权

US10529708B2 Conductivity modulated drain extended MOSFET 有权
公开(公告)号：US10529708B2
公开(公告)日：2020-01-07
申请号：US15871356
申请日：2018-01-15
申请人： Texas Instruments Incorporated
发明人： Aravind C Appaswamy , James P. Di Sarro , Farzan Farbiz
IPC分类号： H01L29/739 , H01L27/07 , H01L29/49
摘要： An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the semiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.

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