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1. 发明授权

US09602841B2 System and method for decoding scalable video coding 有权
公开(公告)号：US09602841B2
公开(公告)日：2017-03-21
申请号：US13663707
申请日：2012-10-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Manu Mathew , Mullangi Venkata Ratna Reddy
IPC分类号： H04N19/88 , H04N19/30
CPC分类号： H04N19/88 , H04N19/30
摘要： A system and method for decoding video encoded using scalable video coding. In one embodiment, a decoder for scalable video coding (SVC) includes an SVC access unit analyzer and decoding logic. The SVC access unit analyzer is configured to examine an SVC access unit prior to layered decoding of the access unit, to determine, based on the examination, what operations the access unit specifies for each layer of the decoding, and to determine, based on the determined operations to be performed for each layer of the decoding, what data to store for use by a subsequent layer of the decoding. The decoding logic is configured to decode the access unit via a plurality of decoding layers; and to store at each decoding layer, for use by a subsequent decoding layer, the data determined by the SVC access unit analyzer to be used by the subsequent decoding layer.

2. 发明授权

US09612962B2 Performing cache bank operations in offset sequences from first bank 有权
公开(公告)号：US09612962B2
公开(公告)日：2017-04-04
申请号：US14539526
申请日：2014-11-12
申请人： Texas Instruments Incorporated
发明人： Hetul Sanghvi , Mullangi Venkata Ratna Reddy , Ajit Deepak Gupte , Arindam Basak
IPC分类号： G06F13/28 , G06F12/08 , H04N19/433 , H04N19/51 , G06F12/0846
CPC分类号： G06F12/0848 , G06F13/28 , G06F2212/282 , H04N19/433 , H04N19/51
摘要： In certain embodiments, methods and systems for multimedia data processing are provided. In an embodiment, a method for processing multimedia data includes defining one or more pixel block regions in a first cache so as to cache a plurality of reference pixel blocks corresponding to reference data. A reference pixel block from among the plurality of reference pixel blocks is assigned to a pixel block region from among the one or more pixel block regions based on a predetermined criterion. The reference pixel block is associated with a tag based on the pixel block region so as to facilitate a search of the reference data in order to process a plurality of pixel blocks associated with a multimedia frame of the multimedia data.

3. 发明授权

US10652582B2 Optimized edge order for de-blocking filter 有权
公开(公告)号：US10652582B2
公开(公告)日：2020-05-12
申请号：US15871713
申请日：2018-01-15
申请人： Texas Instruments Incorporated
发明人： Niraj Nandan , Mullangi Venkata Ratna Reddy
IPC分类号： H04N19/80 , H04N19/423 , H04N19/86
摘要： A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.

4. 发明申请

US20180184125A1 OPTIMIZED EDGE ORDER FOR DE-BLOCKING FILTER 审中-公开
公开(公告)号：US20180184125A1
公开(公告)日：2018-06-28
申请号：US15871713
申请日：2018-01-15
申请人： Texas Instruments Incorporated
发明人： Niraj Nandan , Mullangi Venkata Ratna Reddy
IPC分类号： H04N19/80 , H04N19/423 , H04N19/86
CPC分类号： H04N19/80 , H04N19/423 , H04N19/86
摘要： A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.

5. 发明授权

US11202102B2 Optimized edge order for de-blocking filter 有权
公开(公告)号：US11202102B2
公开(公告)日：2021-12-14
申请号：US16838132
申请日：2020-04-02
申请人： Texas Instruments Incorporated
发明人： Niraj Nandan , Mullangi Venkata Ratna Reddy
IPC分类号： H04N19/80 , H04N19/423 , H04N19/86
摘要： A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.

6. 发明申请

US20150074318A1 METHODS AND SYSTEMS FOR MULTIMEDIA DATA PROCESSING 审中-公开
标题翻译：多媒体数据处理方法与系统
公开(公告)号：US20150074318A1
公开(公告)日：2015-03-12
申请号：US14539526
申请日：2014-11-12
申请人： Texas Instruments Incorporated
发明人： Hetul Sanghvi , Mullangi Venkata Ratna Reddy , Ajit Deepak Gupta , Arindam Basak
IPC分类号： G06F12/08 , G06F13/28
CPC分类号： G06F12/0848 , G06F13/28 , G06F2212/282 , H04N19/433 , H04N19/51
摘要： In certain embodiments, methods and systems for multimedia data processing are provided. In an embodiment, a method for processing multimedia data includes defining one or more pixel block regions in a first cache so as to cache a plurality of reference pixel blocks corresponding to reference data. A reference pixel block from among the plurality of reference pixel blocks is assigned to a pixel block region from among the one or more pixel block regions based on a predetermined criterion. The reference pixel block is associated with a tag based on the pixel block region so as to facilitate a search of the reference data in order to process a plurality of pixel blocks associated with a multimedia frame of the multimedia data.
摘要翻译：在某些实施例中，提供了用于多媒体数据处理的方法和系统。在一个实施例中，一种用于处理多媒体数据的方法包括定义第一高速缓存中的一个或多个像素块区域，以便缓存对应于参考数据的多个参考像素块。基于预定标准，从多个参考像素块中的参考像素块从一个或多个像素块区域中分配给像素块区域。参考像素块基于像素块区域与标签相关联，以便于搜索参考数据，以便处理与多媒体数据的多媒体帧相关联的多个像素块。

7. 发明申请

US20140119436A1 SYSTEM AND METHOD FOR DECODING SCALABLE VIDEO CODING 有权
标题翻译：用于解码可视化视频编码的系统和方法
公开(公告)号：US20140119436A1
公开(公告)日：2014-05-01
申请号：US13663707
申请日：2012-10-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Manu Mathew , Mullangi Venkata Ratna Reddy
IPC分类号： H04N7/26
CPC分类号： H04N19/88 , H04N19/30
摘要： A system and method for decoding video encoded using scalable video coding. In one embodiment, a decoder for scalable video coding (SVC) includes an SVC access unit analyzer and decoding logic. The SVC access unit analyzer is configured to examine an SVC access unit prior to layered decoding of the access unit, to determine, based on the examination, what operations the access unit specifies for each layer of the decoding, and to determine, based on the determined operations to be performed for each layer of the decoding, what data to store for use by a subsequent layer of the decoding. The decoding logic is configured to decode the access unit via a plurality of decoding layers; and to store at each decoding layer, for use by a subsequent decoding layer, the data determined by the SVC access unit analyzer to be used by the subsequent decoding layer.
摘要翻译：一种用于对使用可分级视频编码编码的视频进行解码的系统和方法。在一个实施例中，用于可分级视频编码（SVC）的解码器包括SVC存取单元分析器和解码逻辑。 SVC访问单元分析器被配置为在访问单元的分层解码之前检查SVC访问单元，以基于检查来确定访问单元为每个解码层指定什么操作，并且基于要为每个解码层执行确定的操作，存储哪些数据以供后续解码层使用。解码逻辑被配置为经由多个解码层对存取单元进行解码; 并且在每个解码层存储由后续解码层使用的由SVC存取单元分析器确定的数据由后续解码层使用。

8. 发明申请

US20220070499A1 OPTIMIZED EDGE ORDER FOR DE-BLOCKING FILTER 有权
公开(公告)号：US20220070499A1
公开(公告)日：2022-03-03
申请号：US17523541
申请日：2021-11-10
申请人： Texas Instruments Incorporated
发明人： Niraj Nandan , Mullangi Venkata Ratna Reddy
IPC分类号： H04N19/80 , H04N19/423 , H04N19/86
摘要： A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.

9. 发明申请

US20200236405A1 OPTIMIZED EDGE ORDER FOR DE-BLOCKING FILTER 审中-公开
公开(公告)号：US20200236405A1
公开(公告)日：2020-07-23
申请号：US16838132
申请日：2020-04-02
申请人： Texas Instruments Incorporated
发明人： Niraj Nandan , Mullangi Venkata Ratna Reddy
IPC分类号： H04N19/80 , H04N19/86 , H04N19/423
摘要： A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.

10. 发明授权

US09872044B2 Optimized edge order for de-blocking filter 有权
公开(公告)号：US09872044B2
公开(公告)日：2018-01-16
申请号：US14278697
申请日：2014-05-15
申请人： Texas Instruments Incorporated
发明人： Niraj Nandan , Mullangi Venkata Ratna Reddy
IPC分类号： H04N19/80 , H04N19/423 , H04N19/86
CPC分类号： H04N19/80 , H04N19/423 , H04N19/86
摘要： A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.

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