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1. 发明授权

US10319809B2 Structures to avoid floating resurf layer in high voltage lateral devices 有权
公开(公告)号：US10319809B2
公开(公告)日：2019-06-11
申请号：US15843444
申请日：2017-12-15
申请人： Texas Instruments Incorporated
发明人： Yongxi Zhang , Philip L. Hower , John Lin , Guru Mathur , Scott G. Balster , Constantin Bulucea , Zachary K. Lee , Sameer P. Pendharkar
IPC分类号： H01L29/06 , H01L29/78 , H01L29/10 , H01L23/485 , H01L29/423
摘要： A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

2. 发明申请

US20160254346A1 STRUCTURES TO AVOID FLOATING RESURF LAYER IN HIGH VOLTAGE LATERAL DEVICES 有权
标题翻译：避免在高压侧设备中浮动还原层的结构
公开(公告)号：US20160254346A1
公开(公告)日：2016-09-01
申请号：US14634801
申请日：2015-02-28
申请人： Texas Instruments Incorporated
发明人： Yongxi Zhang , Philip L. Hower , John Lin , Guru Mathur , Scott G. Balster , Constantin Bulucea , Zachary K. Lee , Sameer P. Pendharkar
IPC分类号： H01L29/06 , H01L29/08 , H01L29/78
CPC分类号： H01L29/063 , H01L23/485 , H01L29/0692 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.
摘要翻译：半导体器件包含在漏极漂移区域上具有横向n型漏极漂移区域和p型RESURF区域的LDNMOS晶体管。 RESURF区域延伸到半导体器件的衬底的顶表面。半导体器件包括电耦合在RESURF区域和LDNMOS晶体管的低电压节点之间的分流器。分路可以是RESURF层和LDNMOS晶体管的主体之间的衬底中的p型注入层，并且可以与RESURF层同时注入。分流器可以穿过漏极漂移区域中的从RESURF层到漏极漂移区域下方的衬底的开口。分路可以包括包括触点和金属互连线的金属互连元件。

3. 发明授权

US09397211B2 Lateral MOSFET with buried drain extension layer 有权
标题翻译：具有埋漏极扩展层的横向MOSFET
公开(公告)号：US09397211B2
公开(公告)日：2016-07-19
申请号：US14559239
申请日：2014-12-03
申请人： Texas Instruments Incorporated
发明人： Marie Denison , Philip L. Hower , Sameer Pendharkar
IPC分类号： H01L29/78 , H01L29/06 , H01L29/08 , H01L29/66 , H01L29/10 , H01L21/324 , H01L21/225 , H01L21/761 , H01L21/266 , H01L29/40 , H01L29/423
CPC分类号： H01L29/0634 , H01L21/225 , H01L21/2253 , H01L21/266 , H01L21/324 , H01L21/761 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/0882 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7823 , H01L29/7835
摘要： An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.
摘要翻译：一种集成电路，其包含延伸漏极MOS晶体管，其具有漂移层，在上部RESURF层上并接触漂移层的上表面，以及在漂移层下面的埋入漏极延伸层，该漏极延伸层与漏极的漂移层电连接在通道端处与漂移层分离。可以在通道端处的漂移层和埋漏极延伸部之间形成较低的RESURF层。上部RESURF层，漂移层，下部RESURF层和掩埋漏极延伸中的任何一个可以具有从漏极端到沟道端的渐变掺杂密度。形成包含具有漂移层的延伸漏极MOS晶体管的集成电路的工艺，上部RESURF层和掩埋漏极延伸。

4. 发明申请

US20130277739A1 Integrated Lateral High Voltage Mosfet 有权
标题翻译：集成侧向高电压Mosfet
公开(公告)号：US20130277739A1
公开(公告)日：2013-10-24
申请号：US13922381
申请日：2013-06-20
申请人： Texas Instruments Incorporated
发明人： Marie Denison , Sameer Pendharkar , Philip L. Hower
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L21/265 , H01L21/823814 , H01L27/0922 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1083 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.
摘要翻译：一种包含双漂移层延伸漏极MOS晶体管的集成电路，其上部漂移层沿着两个漂移层的公共长度的至少75％与下部漂移层接触。下漂移层中的平均掺杂密度在上漂移层中的平均掺杂密度的2至10倍。一种形成集成电路的过程，该集成电路包含在体区内具有较低漂移延伸的双漂移层延伸漏极MOS晶体管，以及使用外延工艺电隔离体区的隔离链路。一种形成集成电路的过程，该集成电路包含在主体区域具有较低漂移延伸的双漂移层延伸漏极MOS晶体管和在整体式衬底上电隔离体区的隔离链路。

5. 发明授权

US11152459B2 Lateral MOSFET with buried drain extension layer 有权
公开(公告)号：US11152459B2
公开(公告)日：2021-10-19
申请号：US16735729
申请日：2020-01-07
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Marie Denison , Philip L. Hower , Sameer Pendharkar
IPC分类号： H01L29/06 , H01L29/78 , H01L29/08 , H01L29/66 , H01L29/10 , H01L21/324 , H01L21/225 , H01L21/761 , A61B90/70 , H01L29/40 , H01L21/266 , H01L29/423 , A61J17/00
摘要： An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

6. 发明授权

US10535731B2 Lateral MOSFET with buried drain extension layer 有权
公开(公告)号：US10535731B2
公开(公告)日：2020-01-14
申请号：US15955122
申请日：2018-04-17
申请人： Texas Instruments Incorporated
发明人： Marie Denison , Philip L. Hower , Sameer Pendharkar
IPC分类号： H01L29/06 , H01L29/78 , H01L29/08 , H01L29/66 , H01L29/10 , H01L21/324 , H01L21/225 , H01L21/761 , H01L29/40 , H01L21/266 , H01L29/423
摘要： An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

7. 发明申请

US20160351772A1 VERTICAL THERMOELECTRIC STRUCTURES 审中-公开
标题翻译：垂直热电结构
公开(公告)号：US20160351772A1
公开(公告)日：2016-12-01
申请号：US15162033
申请日：2016-05-23
申请人： Texas Instruments Incorporated
发明人： Barry Jon Male , Philip L. Hower
IPC分类号： H01L35/30 , H01L27/16 , H01L35/22 , H01L35/32
CPC分类号： H01L35/30 , H01L23/38 , H01L27/16 , H01L35/22 , H01L35/32 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at the other end. The lateral thermoelectric elements are thermally isolated by interconnect dielectric materials on the top side and field oxide on the bottom side. When operated in a generator mode, the metal thermal terminals are connected to a heat source and the IC substrate is connected to a heat sink. Thermal power flows through the vertical conduits to the lateral thermoelectric elements, which generate an electrical potential. The electrical potential may be applied to a component or circuit in the IC. The thermoelectric device may be integrated into an IC without adding fabrication cost or complexity.
摘要翻译：公开了一种热电装置，其包括从IC的顶表面突出的金属热端子，其连接到由IC的互连元件制成的垂直导热导管。侧向热电元件在一端连接到垂直导管，并在另一端与IC基板相互散热。侧向热电元件通过顶侧的互连电介质材料和底侧的场氧化物热隔离。当在发电机模式下工作时，金属热端子连接到热源，并且IC基板连接到散热器。热功率流过垂直管道到横向热电元件，产生电位。电位可以施加到IC中的元件或电路。热电装置可以集成到IC中而不增加制造成本或复杂性。

8. 发明授权

US10446734B2 Vertical thermoelectric structures 有权
公开(公告)号：US10446734B2
公开(公告)日：2019-10-15
申请号：US15162033
申请日：2016-05-23
申请人： Texas Instruments Incorporated
发明人： Barry Jon Male , Philip L. Hower
IPC分类号： H01L35/30 , H01L23/38 , H01L35/32 , H01L27/16 , H01L35/22
摘要： A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at the other end. The lateral thermoelectric elements are thermally isolated by interconnect dielectric materials on the top side and field oxide on the bottom side. When operated in a generator mode, the metal thermal terminals are connected to a heat source and the IC substrate is connected to a heat sink. Thermal power flows through the vertical conduits to the lateral thermoelectric elements, which generate an electrical potential. The electrical potential may be applied to a component or circuit in the IC. The thermoelectric device may be integrated into an IC without adding fabrication cost or complexity.

9. 发明授权

US09985095B2 Lateral MOSFET with buried drain extension layer 有权
公开(公告)号：US09985095B2
公开(公告)日：2018-05-29
申请号：US15182658
申请日：2016-06-15
申请人： Texas Instruments Incorporated
发明人： Marie Denison , Philip L. Hower , Sameer Pendharkar
IPC分类号： H01L29/06 , H01L29/78 , H01L29/08 , H01L29/66 , H01L29/10 , H01L21/324 , H01L21/225 , H01L21/761 , H01L21/266 , H01L29/40 , H01L29/423
CPC分类号： H01L29/0634 , H01L21/225 , H01L21/2253 , H01L21/266 , H01L21/324 , H01L21/761 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/0882 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7823 , H01L29/7835
摘要： An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

10. 发明授权

US09843322B2 Integrated high-side driver for P-N bimodal power device 有权
公开(公告)号：US09843322B2
公开(公告)日：2017-12-12
申请号：US15067928
申请日：2016-03-11
申请人： Texas Instruments Incorporated
发明人： Yongxi Zhang , Sameer P. Pendharkar , Philip L. Hower , Salvatore Giombanco , Filippo Marino , Seetharaman Sridhar
IPC分类号： H03L5/00 , H03K17/687 , H01L27/092 , H01L29/06 , H03K19/0185
CPC分类号： H03K19/018521 , H01L21/823807 , H01L21/823814 , H01L27/092 , H01L29/0634 , H01L29/0696 , H01L29/1033 , H01L29/7816 , H01L29/7831 , H03K17/122
摘要： An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

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