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1. 发明申请

US20230061337A1 HIGH VOLTAGE FINGER LAYOUT TRANSISTOR 有权
公开(公告)号：US20230061337A1
公开(公告)日：2023-03-02
申请号：US17463529
申请日：2021-08-31
申请人： Texas Instruments Incorporated
发明人： Jungwoo Joh , Sunglyong Kim , Seetharaman Sridhar , Sameer Pendharkar , James Craig Ondrusek , Srikanth Krishnan
IPC分类号： H01L29/417 , H01L23/482 , H01L27/098
摘要： An integrated circuit, including a source region, a drain region, a channel region between the source region and the drain region, and a gate for inducing a conductive path through the channel region. The integrated circuit also includes structure, proximate a curved length of the gate, for inhibiting current flow along a portion of the channel region.

2. 发明申请

US20150160285A1 Apparatus and Methods for Qualifying HEMT FET Devices 有权
标题翻译：用于限定HEMT FET器件的装置和方法
公开(公告)号：US20150160285A1
公开(公告)日：2015-06-11
申请号：US14547849
申请日：2014-11-19
申请人： Texas Instruments Incorporated
发明人： Jungwoo Joh , Srikanth Krishnan , Sameer Pendharkar
IPC分类号： G01R31/26 , H01L21/78 , H01L29/66 , H01L21/66
CPC分类号： G01R31/2621 , H01L29/2003 , H01L29/7787
摘要： A method includes coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test; for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal, and for each of the test conditions, applying a voltage pulse to the gate terminal, the gate pulse rising only after the drain pulse falls below a predetermined threshold; for a second set of test conditions, applying a voltage pulse to the drain terminal, and applying a voltage pulse to the gate terminal, the drain pulse generator and the gate pulse generator both being active so that there is some overlap; and measuring the drain current into the power transistor device under test. An apparatus is disclosed.
摘要翻译：一种方法包括将栅极脉冲发生器耦合到被测功率晶体管器件的栅极端子，将漏极脉冲发生器耦合到被测功率晶体管器件的漏极端子; 对于第一组测试条件，激活用于每个测试条件的漏极脉冲发生器以向漏极端施加电压脉冲，并且对于每个测试条件，向栅极端施加电压脉冲，门脉冲上升仅在漏极脉冲下降到预定阈值以下之前; 对于第二组测试条件，向漏极端子施加电压脉冲，并向栅极端施加电压脉冲，漏极脉冲发生器和栅极脉冲发生器都处于活动状态，使得存在一些重叠; 并测量进入被测功率晶体管器件的漏极电流。公开了一种装置。

3. 发明授权

US09476933B2 Apparatus and methods for qualifying HEMT FET devices 有权
标题翻译：用于限定HEMT FET器件的装置和方法
公开(公告)号：US09476933B2
公开(公告)日：2016-10-25
申请号：US14547849
申请日：2014-11-19
申请人： Texas Instruments Incorporated
发明人： Jungwoo Joh , Srikanth Krishnan , Sameer Pendharkar
IPC分类号： G01R31/02 , G01R31/26 , H01L29/778 , H01L29/20
CPC分类号： G01R31/2621 , H01L29/2003 , H01L29/7787
摘要： A method includes coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test; for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal, and for each of the test conditions, applying a voltage pulse to the gate terminal, the gate pulse rising only after the drain pulse falls below a predetermined threshold; for a second set of test conditions, applying a voltage pulse to the drain terminal, and applying a voltage pulse to the gate terminal, the drain pulse generator and the gate pulse generator both being active so that there is some overlap; and measuring the drain current into the power transistor device under test. An apparatus is disclosed.
摘要翻译：一种方法包括将栅极脉冲发生器耦合到被测功率晶体管器件的栅极端子，将漏极脉冲发生器耦合到被测功率晶体管器件的漏极端子; 对于第一组测试条件，激活用于每个测试条件的漏极脉冲发生器以向漏极端施加电压脉冲，并且对于每个测试条件，向栅极端施加电压脉冲，门脉冲上升仅在漏极脉冲下降到预定阈值以下之前; 对于第二组测试条件，向漏极端子施加电压脉冲，并向栅极端施加电压脉冲，漏极脉冲发生器和栅极脉冲发生器都处于活动状态，使得存在一些重叠; 并测量进入被测功率晶体管器件的漏极电流。公开了一种装置。

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