专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10037295B2 Apparatus and methods for generating a selection signal to perform an arbitration in a single cycle between multiple signal inputs having respective data to send 有权
公开(公告)号：US10037295B2
公开(公告)日：2018-07-31
申请号：US15367218
申请日：2016-12-02
申请人： The Regents of the University of Michigan
发明人： Supreet Jeloka , Sandunmalee Nilmini Abeyratne , Ronald George Dreslinski , Reetuparna Das , Trevor Nigel Mudge , David Theodore Blaauw
IPC分类号： G06F13/00 , G06F13/40 , G06F13/374 , G11C7/10 , H03K17/693 , G06F13/16
CPC分类号： G06F13/4022 , G06F13/1642 , G06F13/374 , G06F2213/0038 , G11C7/10 , G11C7/1012 , H03K17/693
摘要： An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).

2. 发明授权

US09514074B2 Single cycle arbitration within an interconnect 有权
标题翻译：互连中的单周期仲裁
公开(公告)号：US09514074B2
公开(公告)日：2016-12-06
申请号：US13940915
申请日：2013-07-12
申请人： The Regents of the University of Michigan
发明人： Supreet Jeloka , Sandunmalee Nilmini Abeyratne , Ronald George Dreslinski , Reetuparna Das , Trevor Nigel Mudge , David Theodore Blaauw
IPC分类号： G06F13/00 , G06F13/374 , G06F13/40 , G11C7/10 , H03K17/693
CPC分类号： G06F13/4022 , G06F13/1642 , G06F13/374 , G06F2213/0038 , G11C7/10 , G11C7/1012 , H03K17/693
摘要： An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).
摘要翻译：集成电路内的互连提供仲裁以选择用于连接到信号输出的多个信号输入中的一个。应用的仲裁使用时间戳值形式的第一仲裁参数值，并且如果两个或更多个信号输入共享这样的时间戳值，则以最小最近许可值的形式使用第二仲裁参数。选择应用于与授予对信号输出的访问时的每个信号输入相关联的时间戳值的时间增量以反映与该信号输入相关联的服务质量。当在时间戳值之间进行比较时，优先考虑最低时间戳值。大的时间增量值对应于低优先级（服务质量）。

3. 发明授权

US09396795B1 Storage device supporting logical operations, methods and storage medium 有权
标题翻译：存储设备支持逻辑操作，方法和存储介质
公开(公告)号：US09396795B1
公开(公告)日：2016-07-19
申请号：US14586076
申请日：2014-12-30
申请人： The Regents of the University of Michigan
发明人： Supreet Jeloka , David Theodore Blaauw
IPC分类号： G11C15/04 , G11C11/419
CPC分类号： G11C15/043 , G06F17/30982 , G11C7/067 , G11C7/1006 , G11C11/419 , G11C15/04
摘要： A storage device has a plurality of storage cells for storing data values. Control circuitry is provided to simultaneously couple at least two cells to at least one common signal line. Sensing circuitry is provided to sense a signal on the at least one common signal line, which indicates a result of a logical operation applied to the data values stored in each of the at least two storage cells. This allows logic operations such as AND, OR, XOR, etc. to be performed within a storage device so that it is not necessary to read out each data value independently and transfer each data value to a separate processing circuit in order to find the result of the logical operation. This helps to improve performance within a data processing apparatus having the storage device.
摘要翻译：存储装置具有用于存储数据值的多个存储单元。提供控制电路以同时将至少两个单元耦合到至少一个公共信号线。提供感测电路以感测至少一个公共信号线上的信号，其指示应用于存储在至少两个存储单元中的每一个中的数据值的逻辑运算的结果。这允许在存储设备内执行诸如AND，OR，XOR等的逻辑操作，使得不需要独立地读出每个数据值，并将每个数据值传送到单独的处理电路以便找到结果的逻辑运算。这有助于提高具有存储装置的数据处理装置中的性能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式