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    • 2. 发明申请
    • CIRCUIT OF A NODE AND METHOD FOR TRANSIT TIME MEASUREMENT IN A RADIO NETWORK
    • 无线电网络中用于传输时间测量的节点和方法的电路
    • US20100329139A1
    • 2010-12-30
    • US12824874
    • 2010-06-28
    • Tilo FERCHLANDMichael SCHMIDTEric SACHSE
    • Tilo FERCHLANDMichael SCHMIDTEric SACHSE
    • H04J3/14
    • H04W4/02G01S5/0289G01S13/765H04J3/0682H04L1/1848H04L1/188H04L1/205H04W56/0055H04W56/0065
    • A circuit of a node in a radio network and method for transit time measurement between a first node and a second node of a radio network is provided. A frame is transmitted by the first node, wherein the frame requires an acknowledgment of reception by the second node. A first point in time of the transmission of the frame is established by the first node by a time counter. The frame is received by the second node at a second point in time. The acknowledgment is transmitted by the second node to the first node at a third point in time, wherein the third point in time depends on the second point in time by a predetermined time interval between the second point in time and the third point in time. A fourth point in time is established by the first node by the time counter when the acknowledgment is received. The transit time or the change in transit time is determined from the first point in time established by the time counter and from the established fourth point in time and from the predetermined time interval.
    • 提供无线电网络中的节点的电路和无线电网络的第一节点和第二节点之间的传输时间测量方法。 帧由第一节点发送,其中帧需要由第二节点接收的确认。 帧的发送的第一时间点由第一节点通过时间计数器建立。 帧在第二时间点由第二节点接收。 所述确认在第三时间点由所述第二节点发送到所述第一节点,其中所述第三时间点在所述第二时间点上依赖于所述第二时间点在所述第二时间点和所述第三时间点之间的预定时间间隔。 当接收到确认时,由第一节点通过时间计数器建立第四时间点。 从通过时间计数器建立的第一时间点和从建立的第四时间点到预定的时间间隔确定通行时间或通行时间的变化。
    • 5. 发明申请
    • INTEGRATED CIRCUIT AND STANDARD CELL FOR AN INTEGRATED CIRCUIT
    • 集成电路的集成电路和标准电路
    • US20100321063A1
    • 2010-12-23
    • US12817709
    • 2010-06-17
    • Tilo FERCHLANDThorsten RIEDELMatthias VORWERK
    • Tilo FERCHLANDThorsten RIEDELMatthias VORWERK
    • H03K19/21
    • H03K19/21
    • An integrated circuit and a standard cell of an integrated circuit, having a master-slave flip-flop, having a comparator logic at whose inputs the input signal of the master-slave flip-flop, the inverted input signal of the master-slave flip-flop, the output signal of the master-slave flip-flop, and the inverted output signal of the master-slave flip-flops are present, wherein the master-slave flip-flop has a master flip-flop and a slave flip-flop, wherein the slave flip-flop has a first inverting element and a second inverting element. Whereby for feedback, an output of the first inverting element is connected to an input of the second inverting element and an output of the second inverting element to an input of the first inverting element. Wherein, to output the output signal and the inverted output signal of the master-slave flip-flop, it is possible to connect the output and the input of the second inverting element to the inputs of the comparator logic so that the second inverting element and the comparator logic and an inverter form an exclusive-OR operation of the standard cell.
    • 集成电路和具有主从触发器的集成电路的标准单元,其具有比较器逻辑,其输入端为主从触发器的输入信号,主从触发器的反相输入信号 存在主从触发器的输出信号和主从触发器的反相输出信号,其中主从触发器具有主触发器和从触发器, 其中从触发器具有第一反相元件和第二反相元件。 由此,对于反馈,第一反相元件的输出端连接到第二反相元件的输入端和第二反相元件的输出端到第一反相元件的输入端。 其中,为了输出主从触发器的输出信号和反相输出信号,可以将第二反相元件的输出和输入连接到比较器逻辑的输入,使得第二反相元件和 比较器逻辑和逆变器形成标准单元的异或运算。