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1. 发明申请

US20110029760A1 NON-ATOMIC SCHEDULING OF MICRO-OPERATIONS TO PERFORM ROUND INSTRUCTION 有权
标题翻译：微操作的非原则性调度来执行指令
公开(公告)号：US20110029760A1
公开(公告)日：2011-02-03
申请号：US12783769
申请日：2010-05-20
申请人： Tom Elmer , Terry Parks
发明人： Tom Elmer , Terry Parks
IPC分类号： G06F9/40 , G06F9/44 , G06F9/30
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/3017 , G06F9/3836
摘要： A microprocessor executes an instruction specifying a floating-point input operand having a predetermined size and that instructs the microprocessor to round the floating-point input operand to an integer value using a rounding mode and to return a floating-point result having the same predetermined size. An instruction translator translates the instruction into first and second microinstructions. An execution unit executes the first and second microinstructions. The first microinstruction receives as an input operand the instruction floating-point input operand and generates an intermediate result from the input operand. The second microinstruction receives as an input operand the intermediate result of the first microinstruction and generates the floating-point result of the instruction from the intermediate result. The intermediate result is the same predetermined size as the instruction floating-point input operand. The microprocessor executes the first and second microinstructions such that the commencement of their executions may have indeterminate separation in time.
摘要翻译：微处理器执行指定具有预定大小的浮点输入操作数的指令，并指示微处理器使用舍入模式将浮点输入操作数舍入到整数值，并返回具有相同预定大小的浮点结果。指令翻译器将指令转换为第一和第二微指令。执行单元执行第一和第二微指令。第一个微指令作为输入操作数接收指令浮点输入操作数，并从输入操作数生成中间结果。第二微指令作为输入操作数接收第一微指令的中间结果，并从中间结果生成指令的浮点结果。中间结果与指令浮点输入操作数相同。微处理器执行第一和第二微指令，使得其执行的开始可能在时间上具有不确定的分离。

2. 发明授权

US08046400B2 Apparatus and method for optimizing the performance of x87 floating point addition instructions in a microprocessor 有权
标题翻译：用于优化微处理器中x87浮点加法指令性能的装置和方法
公开(公告)号：US08046400B2
公开(公告)日：2011-10-25
申请号：US12100583
申请日：2008-04-10
申请人： Tom Elmer , Terry Parks
发明人： Tom Elmer , Terry Parks
IPC分类号： G06F7/485
CPC分类号： G06F7/49942 , G06F9/30014 , G06F9/30065 , G06F9/32 , G06F9/3836 , G06F9/3867
摘要： A microprocessor having a Precision Control (PC) field, an instruction dispatcher, and a Floating Point unit (FPU). The FPU receives an FP Add instruction from the instruction dispatcher, and generates a sum from its addends. The FPU determines whether any conditions exist in the addends with respect to their contribution to a rounding determination and relative to the PC field. If none of the conditions exists, the FPU makes the rounding determination based on the smaller addend and the PC field, and selectively rounds the sum based on the rounding determination. If any conditions exist, the FPU saves the sum and rounding information derived from the addends, and signals the instruction dispatcher to re-dispatch the instruction. On re-dispatch, the FPU makes the rounding determination based on the saved rounding information and the PC field, and selectively rounds the sum based on the rounding determination.
摘要翻译：具有精密控制（PC）场，指令分配器和浮点单元（FPU）的微处理器。 FPU从指令分派器接收FP Add指令，并从其加数中生成一个和。 FPU确定加数中对于舍入确定的贡献以及相对于PC领域是否存在任何条件。如果没有条件存在，则FPU基于较小的加数和PC字段进行舍入确定，并且基于舍入确定选择性地舍入和。如果存在任何条件，FPU将保存从加数中导出的和和舍入信息，并向指令分配器发出信号以重新发送指令。在重新调度时，FPU根据保存的舍入信息和PC字段进行舍入确定，并根据舍入确定选择性地舍入和。

3. 发明申请

US20050273579A1 METHOD AND APPARATUS FOR MAINTAINING STATUS COHERENCY BETWEEN QUEUE-SEPARATED FUNCTIONAL UNITS 有权
标题翻译：维持分离功能单元之间的状态相关性的方法和装置
公开(公告)号：US20050273579A1
公开(公告)日：2005-12-08
申请号：US10279213
申请日：2002-10-23
申请人： Tom Elmer
发明人： Tom Elmer
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3885
摘要： An apparatus and method in a microprocessor having two unaligned functional unit pipelines which enables an instruction queue for the second pipeline to be placed at an intermediate pipeline stage rather than after the stage in the first pipeline that retires instructions. The apparatus maintains coherency between the status of each instruction in the queue relative to its status in the first pipeline. The status comprises an age of the instruction and a valid bit. The age specifies the stage in the first pipeline in which the instruction resides. The apparatus includes logic for updating the age and valid bit based on whether the first pipeline is stalled, on valid bits from the first pipeline, and on whether the queue is downshifting. The microprocessor selectively updates its user-visible state with the instruction execution results from the second functional unit based on the instruction age and valid bit.
摘要翻译：具有两个未对准功能单元管线的微处理器中的装置和方法，其使第二管线的指令队列能够放置在中间流水线阶段，而不是在退出指令的第一管道中的阶段之后。该装置保持队列中每条指令的状态相对于其在第一管道中的状态之间的一致性。状态包括指令的年龄和有效位。年龄指定指令所在的第一个管道中的阶段。该装置包括用于基于第一流水线是否停止，来自第一流水线的有效比特以及该队列是否在下移位来更新年龄和有效比特的逻辑。微处理器基于指令时间和有效位，用来自第二功能单元的指令执行结果选择性地更新其用户可见状态。

4. 发明授权

US08620983B2 Leading sign digit predictor for floating point near subtractor 有权
标题翻译：浮点附近减法器的前导符号数字预测器
公开(公告)号：US08620983B2
公开(公告)日：2013-12-31
申请号：US12985180
申请日：2011-01-05
申请人： Tom Elmer
发明人： Tom Elmer
IPC分类号： G06F7/42 , G06F7/00
CPC分类号： G06F7/485
摘要： An apparatus for predicting leading sign digits in a negative difference includes a comparator that determines a larger of two numbers that differ in magnitude by not more than one digit position. The larger of the two numbers is designated as the subtrahend and the smaller as the minuend. Wires and logic align the subtrahend relative to the minuend by the not more than one digit position and invert the aligned subtrahend. A plurality of NAND gates performs a Boolean NAND function of corresponding digits of the minuend and the aligned inverted subtrahend to produce a prediction string of bits. A zero value is assigned to the most significant bit of the prediction string. A string of leading zeros of the prediction string predicts a corresponding string of leading sign digits of a negative difference of the minuend and aligned subtrahend.
摘要翻译：用于以负差预测前导符号数字的装置包括比较器，其确定大小不同不超过一个数字位置的两个数字中较大的数字。两个数字中的较大的数字被指定为减数，小数被指定为被减数。电线和逻辑将减法相对于限制器对齐不超过一个数字位置，并反转对准的减法器。多个NAND门执行微处理器和对齐的反向减法相关数字的布尔NAND功能，以产生位的预测串。零值被分配给预测串的最高有效位。预测串的前导零的一串预测了一个对应的引导符号数字串，该位数是减法和对齐的减法的负差值。

5. 发明申请

US20090259708A1 APPARATUS AND METHOD FOR OPTIMIZING THE PERFORMANCE OF X87 FLOATING POINT ADDITION INSTRUCTIONS IN A MICROPROCESSOR 有权
标题翻译：用于优化微波处理器中X87漂浮点附加指令性能的装置和方法
公开(公告)号：US20090259708A1
公开(公告)日：2009-10-15
申请号：US12100583
申请日：2008-04-10
申请人： Tom Elmer , Terry Parks
发明人： Tom Elmer , Terry Parks
IPC分类号： G06F7/483
CPC分类号： G06F7/49942 , G06F9/30014 , G06F9/30065 , G06F9/32 , G06F9/3836 , G06F9/3867
摘要： A microprocessor having a Precision Control (PC) field, an instruction dispatcher, and a Floating Point unit (FPU). The FPU receives an FP Add instruction from the instruction dispatcher, and generates a sum from its addends. The FPU determines whether any conditions exist in the addends with respect to their contribution to a rounding determination and relative to the PC field. If none of the conditions exists, the FPU makes the rounding determination based on the smaller addend and the PC field, and selectively rounds the sum based on the rounding determination. If any conditions exist, the FPU saves the sum and rounding information derived from the addends, and signals the instruction dispatcher to re-dispatch the instruction. On re-dispatch, the FPU makes the rounding determination based on the saved rounding information and the PC field, and selectively rounds the sum based on the rounding determination.
摘要翻译：具有精密控制（PC）场，指令分配器和浮点单元（FPU）的微处理器。 FPU从指令分派器接收FP Add指令，并从其加数中生成一个和。 FPU确定加数中对于舍入确定的贡献以及相对于PC领域是否存在任何条件。如果没有条件存在，则FPU基于较小的加数和PC字段进行舍入确定，并且基于舍入确定选择性地舍入和。如果存在任何条件，FPU将保存从加数中导出的和和舍入信息，并向指令分配器发出信号以重新发送指令。在重新调度时，FPU根据保存的舍入信息和PC字段进行舍入确定，并根据舍入确定选择性地舍入和。

6. 发明授权

US08386755B2 Non-atomic scheduling of micro-operations to perform round instruction 有权
标题翻译：非原子调度微操作执行圆指令
公开(公告)号：US08386755B2
公开(公告)日：2013-02-26
申请号：US12783769
申请日：2010-05-20
申请人： Tom Elmer , Terry Parks
发明人： Tom Elmer , Terry Parks
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/3017 , G06F9/3836
摘要： A microprocessor executes an instruction specifying a floating-point input operand having a predetermined size and that instructs the microprocessor to round the floating-point input operand to an integer value using a rounding mode and to return a floating-point result having the same predetermined size. An instruction translator translates the instruction into first and second microinstructions. An execution unit executes the first and second microinstructions. The first microinstruction receives as an input operand the instruction floating-point input operand and generates an intermediate result from the input operand. The second microinstruction receives as an input operand the intermediate result of the first microinstruction and generates the floating-point result of the instruction from the intermediate result. The intermediate result is the same predetermined size as the instruction floating-point input operand. The microprocessor executes the first and second microinstructions such that the commencement of their executions may have indeterminate separation in time.
摘要翻译：微处理器执行指定具有预定大小的浮点输入操作数的指令，并指示微处理器使用舍入模式将浮点输入操作数舍入到整数值，并返回具有相同预定大小的浮点结果。指令翻译器将指令转换为第一和第二微指令。执行单元执行第一和第二微指令。第一个微指令作为输入操作数接收指令浮点输入操作数，并从输入操作数生成中间结果。第二微指令作为输入操作数接收第一微指令的中间结果，并从中间结果生成指令的浮点结果。中间结果与指令浮点输入操作数相同。微处理器执行第一和第二微指令，使得其执行的开始可能在时间上具有不确定的分离。

7. 发明申请

US20120173597A1 LEADING SIGN DIGIT PREDICTOR FOR FLOATING POINT NEAR SUBTRACTOR 有权
标题翻译：引导符号数字预测器，用于浮动点附近的旁路
公开(公告)号：US20120173597A1
公开(公告)日：2012-07-05
申请号：US12985180
申请日：2011-01-05
申请人： Tom Elmer
发明人： Tom Elmer
IPC分类号： G06F7/485 , G06F7/02
CPC分类号： G06F7/485
摘要： An apparatus for predicting leading sign digits in a negative difference includes a comparator that determines a larger of two numbers that differ in magnitude by not more than one digit position. The larger of the two numbers is designated as the subtrahend and the smaller as the minuend. Wires and logic align the subtrahend relative to the minuend by the not more than one digit position and invert the aligned subtrahend. A plurality of NAND gates performs a Boolean NAND function of corresponding digits of the minuend and the aligned inverted subtrahend to produce a prediction string of bits. A zero value is assigned to the most significant bit of the prediction string. A string of leading zeros of the prediction string predicts a corresponding string of leading sign digits of a negative difference of the minuend and aligned subtrahend.
摘要翻译：用于以负差预测前导符号数字的装置包括比较器，其确定大小不同不超过一个数字位置的两个数字中较大的数字。两个数字中的较大的数字被指定为减数，小数被指定为被减数。电线和逻辑将减法相对于限制器对齐不超过一个数字位置，并反转对准的减法器。多个NAND门执行微处理器和对齐的反向减法相关数字的布尔NAND功能，以产生位的预测串。零值被分配给预测串的最高有效位。预测串的前导零的一串预测了一个对应的引导符号数字串，该位数是减法和对齐的减法的负差值。

8. 发明授权

US06983358B2 Method and apparatus for maintaining status coherency between queue-separated functional units 有权
标题翻译：用于维护队列分离的功能单元之间的状态一致性的方法和装置
公开(公告)号：US06983358B2
公开(公告)日：2006-01-03
申请号：US10279213
申请日：2002-10-23
申请人： Tom Elmer
发明人： Tom Elmer
IPC分类号： G08F9/38
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3885
摘要： An apparatus and method in a microprocessor having two unaligned functional unit pipelines which enables an instruction queue for the second pipeline to be placed at an intermediate pipeline stage rather than after the stage in the first pipeline that retires instructions. The apparatus maintains coherency between the status of each instruction in the queue relative to its status in the first pipeline. The status comprises an age of the instruction and a valid bit. The age specifies the stage in the first pipeline in which the instruction resides. The apparatus includes logic for updating the age and valid bit based on whether the first pipeline is stalled, on valid bits from the first pipeline, and on whether the queue is downshifting. The microprocessor selectively updates its user-visible state with the instruction execution results from the second functional unit based on the instruction age and valid bit.
摘要翻译：具有两个未对准功能单元管线的微处理器中的装置和方法，其使第二管线的指令队列能够放置在中间流水线阶段，而不是在退出指令的第一管道中的阶段之后。该装置保持队列中每条指令的状态相对于其在第一管道中的状态之间的一致性。状态包括指令的年龄和有效位。年龄指定指令所在的第一个管道中的阶段。该装置包括用于基于第一流水线是否停止，来自第一流水线的有效比特以及该队列是否在下移位来更新年龄和有效比特的逻辑。微处理器基于指令时间和有效位，用来自第二功能单元的指令执行结果选择性地更新其用户可见状态。

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