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    • 1. 发明授权
    • Display panel
    • 显示面板
    • US07830084B2
    • 2010-11-09
    • US11541005
    • 2006-09-29
    • Tomoyuki ShirasakiMinoru KumagaiHiroyasu YamadaTsuyoshi OzakiJun Ogura
    • Tomoyuki ShirasakiMinoru KumagaiHiroyasu YamadaTsuyoshi OzakiJun Ogura
    • H01J1/62H01J63/04
    • H01L27/3246G09G3/325G09G2300/0842G09G2300/0866G09G2320/0223H01L2251/558
    • A display panel including a plurality of pixels. Each pixel includes: a light emitting element; a pixel circuit having a driving transistor connected to the light emitting element in series; a data line to which a data current is supplied through the pixel circuit; a scanning line for selecting the pixel circuit; a first insulation film to cover the data line; and a second insulation film made of a material different from the first insulation film, to cover the data line and the first insulation film, wherein the following expression is satisfied. C total 20 ≦ ɛ 0 ⁢ ɛ a ⁢ ɛ b ɛ a ⁢ D b + ɛ b ⁢ D a ≦ C total 5 Ctotal: parasitic capacitance of whole path to data line through pixel circuit; ∈0: vacuum dielectric constant; ∈a: relative dielectric constant of first insulation film; Da: first insulation film thickness; ∈b: relative dielectric constant of second insulation film; Db: second insulation film thickness.
    • 包括多个像素的显示面板。 每个像素包括:发光元件; 具有与发光元件串联连接的驱动晶体管的像素电路; 通过像素电路提供数据电流的数据线; 用于选择像素电路的扫描线; 覆盖数据线的第一绝缘膜; 以及由不同于第一绝缘膜的材料制成的覆盖数据线和第一绝缘膜的第二绝缘膜,其中满足以下表达式。 C总共20≦̸ ɛ0εaεεbɛa D b +ɛb D a≦̸ C总共5个Ctotal:通过像素电路的数据线的整个路径的寄生电容; ∈0:真空介电常数; ∈a:第一绝缘膜的相对介电常数; Da:第一绝缘膜厚度; ∈b:第二绝缘膜的相对介电常数; Db:第二绝缘膜厚度。
    • 4. 发明申请
    • TRANSISTOR ARRAY SUBSTRATE AND DISPLAY PANEL
    • 晶体管阵列和显示面板
    • US20090239321A1
    • 2009-09-24
    • US12477710
    • 2009-06-03
    • Satoru SHIMODATomoyuki ShirasakiJun OguraMinoru Kumagai
    • Satoru SHIMODATomoyuki ShirasakiJun OguraMinoru Kumagai
    • H01L21/02H01L33/00
    • H01L27/124
    • A transistor array substrate includes a plurality of driving transistors which are arrayed in a matrix on a substrate. The driving transistor has a gate, a source, a drain, and a gate insulating film inserted between the gate, and the source and drain. A plurality of signal lines are patterned together with the gates of the driving transistors and arrayed to run in a predetermined direction on the substrate. A plurality of supply lines are patterned together with the sources and drains of the driving transistors and arrayed to cross the signal lines via the gate insulating film. The supply line is electrically connected to one of the source and the drain of the driving transistor. A plurality of feed interconnections are formed on the supply lines along the supply lines, respectively.
    • 晶体管阵列基板包括在基板上排列成矩阵的多个驱动晶体管。 驱动晶体管具有插入栅极和源极和漏极之间的栅极,源极,漏极和栅极绝缘膜。 多个信号线与驱动晶体管的栅极一起被图案化并排列成在衬底上沿预定方向运行。 多个供电线与驱动晶体管的源极和漏极一起被图案化,并被排列成经由栅极绝缘膜与信号线交叉。 电源线与驱动晶体管的源极和漏极之一电连接。 在供给线上分别沿供给线形成多个供给互连。
    • 7. 发明授权
    • Display panel
    • 显示面板
    • US07446338B2
    • 2008-11-04
    • US11235579
    • 2005-09-26
    • Tomoyuki ShirasakiTsuyoshi OzakiJun Ogura
    • Tomoyuki ShirasakiTsuyoshi OzakiJun Ogura
    • H01L29/04
    • H01L27/3279H01L27/3246H01L27/3262H01L51/56
    • A display panel includes a transistor array substrate which has a plurality of pixels and is formed by providing a plurality of transistors for each pixel, each of the transistor having a gate, a gate insulating film, a source, and a drain. A plurality of interconnections are formed to project to a surface of the transistor array substrate and arrayed in parallel to each other. A plurality of pixel electrodes are provided for each pixel and arrayed between the interconnections on the surface of the transistor array substrate along the interconnections. Each of a plurality of light-emitting layers is formed on each pixel electrode. A counter electrode is stacked on the light-emitting layer.
    • 显示面板包括晶体管阵列基板,其具有多个像素,并且通过为每个像素提供多个晶体管而形成,每个晶体管具有栅极,栅极绝缘膜,源极和漏极。 多个互连形成为突出到晶体管阵列基板的表面并彼此平行排列。 为每个像素提供多个像素电极,并且沿着互连排列在晶体管阵列基板的表面上的互连之间。 在各像素电极上形成有多个发光层。 反电极堆叠在发光层上。