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1. 发明授权

US08878270B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08878270B2
公开(公告)日：2014-11-04
申请号：US13443928
申请日：2012-04-11
申请人： Toshihiko Saito
发明人： Toshihiko Saito
IPC分类号： H01L31/18 , H01L49/02 , H01L29/786 , H01L27/02 , H01L27/12 , H01L21/84 , H01L27/108
CPC分类号： H01L29/7869 , H01L21/84 , H01L27/0288 , H01L27/10876 , H01L27/10891 , H01L27/1203 , H01L28/60 , H01L28/86 , H01L28/90
摘要： A semiconductor memory device including a bit line, a word line, a transistor, and a capacitor is provided. The transistor includes source and drain electrodes; an oxide semiconductor film in contact with at least both top surfaces of the source and drain electrodes; a gate insulating film in contact with at least a top surface of the oxide semiconductor film; a gate electrode which overlaps with the oxide semiconductor film with the gate insulating film provided therebetween; and an insulating film covering the source and drain electrodes, the gate insulating film, and the gate electrode. The transistor is provided in a mesh of a netlike conductive film when seen from the above. Here, the drain electrode and the netlike conductive film serve as one and the other of a pair of capacitor electrodes of the capacitor. A dielectric film of the capacitor includes at least the insulating film.
摘要翻译：提供了包括位线，字线，晶体管和电容器的半导体存储器件。晶体管包括源极和漏极; 与所述源极和漏极的至少两个顶表面接触的氧化物半导体膜; 与所述氧化物半导体膜的至少顶面接触的栅极绝缘膜; 与所述氧化物半导体膜重叠的栅电极，其间设置有所述栅极绝缘膜; 以及覆盖源极和漏极，栅极绝缘膜和栅电极的绝缘膜。当从上面看时，晶体管设置在网状导电膜的网格中。这里，漏电极和网状导电膜用作电容器的一对电容器电极中的一个和另一个。电容器的电介质膜至少包括绝缘膜。

2. 发明授权

US08820047B2 Combustion burner 有权
公开(公告)号：US08820047B2
公开(公告)日：2014-09-02
申请号：US12743315
申请日：2008-10-30
申请人： Toshihiko Saito , Koichi Ishizaka , Satoshi Tanimura
发明人： Toshihiko Saito , Koichi Ishizaka , Satoshi Tanimura
IPC分类号： F02C3/30 , F23R3/14 , F23R3/28 , F02C7/22
CPC分类号： F23R3/283 , F02C3/30 , F02C3/305 , F02C7/22 , F23R3/14 , F23R3/38 , F23R2900/00004 , Y02T50/675
摘要： A combustion burner 10A according to one embodiment of the present invention includes: a fuel nozzle 110; a burner tube 120 forming the air passage 111 between the burner tube 120 and the fuel nozzle 110; swirler vanes (swirler vanes) 130 arranged in a plurality of positions in the circumferential direction on the external circumferential surface of the fuel nozzle 110, each extending along the axial direction of the fuel nozzle 110, and gradually curving from upstream toward downstream; and a liquid fuel injecting hole 133A from which a liquid fuel is injected to a surface of each of the swirler vanes 130. The combustion burner 10A also includes multi-purpose injecting holes 11-1 to 11-3 as a cooling unit that cools a part of a vane pressure surface 132a of the swirler vane 130 on which the liquid fuel LF hits. Water is injected through the multi-purpose injecting holes 11-1 to 11-3 to form a water film 15A on the vane pressure surface 132a, whereby a combustion temperature is reduced and formation of carbon deposit is prevented.

3. 发明授权

US08767443B2 Semiconductor memory device and method for inspecting the same 有权
标题翻译：半导体存储器件及其检测方法
公开(公告)号：US08767443B2
公开(公告)日：2014-07-01
申请号：US13235967
申请日：2011-09-19
申请人： Toshihiko Saito
发明人： Toshihiko Saito
IPC分类号： G11C11/24
CPC分类号： G11C16/26 , G11C11/403 , G11C11/404 , G11C16/0433
摘要： When the threshold voltage Vth of the transistor in the memory cell is within the allowable range is determined, a memory cell which does not have sufficient data retention characteristics is eliminated. In order to eliminate such a memory cell, the potential of a gate of the transistor is kept at an appropriate potential VGM and the potential of a drain of the transistor is set higher than or equal to VGM. When data is written to the memory cell in this state, the potential of a source of the transistor is expressed as a formula including the threshold voltage Vth, (VGM−Vth). By comparison between the level of the potential and the level of a reference potential, whether the threshold voltage Vth is within the allowable range can be determined.
摘要翻译：当确定存储单元中的晶体管的阈值电压Vth在允许范围内时，消除了不具有足够数据保持特性的存储单元。为了消除这种存储单元，晶体管的栅极的电位保持在适当的电位VGM，并且晶体管的漏极的电位被设置为高于或等于VGM。当在该状态下将数据写入存储单元时，晶体管的源极的电位被表示为包括阈值电压Vth（VGM-Vth）的公式。通过比较电位的电平和参考电位的电平，可以确定阈值电压Vth是否在容许范围内。

4. 发明授权

US08709889B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08709889B2
公开(公告)日：2014-04-29
申请号：US13471667
申请日：2012-05-15
申请人： Toshihiko Saito
发明人： Toshihiko Saito
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L29/7869 , G11C11/404 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/84 , H01L27/1156 , H01L27/1207 , H01L27/1225
摘要： A memory cell therein includes a first transistor and a capacitor and stores data corresponding to a potential held in the capacitor. The first transistor includes a pair of electrodes, an insulating film in contact with side surfaces of the electrodes, a first gate electrode provided between the electrodes with the insulating film provided between the first gate electrode and each electrode and whose top surface is at a lower level than top surfaces of the electrodes, a first gate insulating film over the first gate electrode, an oxide semiconductor film in contact with the first gate insulating film and the electrodes, a second gate insulating film at least over the oxide semiconductor film, and a second gate electrode over the oxide semiconductor film with the second gate insulating film provided therebetween. The capacitor is connected to the first transistor through one of the electrodes.
摘要翻译：其中的存储单元包括第一晶体管和电容器，并且存储对应于保持在电容器中的电位的数据。所述第一晶体管包括一对电极，与所述电极的侧面接触的绝缘膜，设置在所述电极之间的第一栅电极，所述绝缘膜设置在所述第一栅电极与每个电极之间，并且其顶表面处于下部比第一栅极电极上的第一栅极绝缘膜，与第一栅极绝缘膜和电极接触的氧化物半导体膜，至少在氧化物半导体膜上的第二栅极绝缘膜，和第二栅极电极在氧化物半导体膜上方，其间设置有第二栅极绝缘膜。电容器通过其中一个电极连接到第一晶体管。

5. 发明授权

US08482974B2 Semiconductor memory device and method for driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US08482974B2
公开(公告)日：2013-07-09
申请号：US13022292
申请日：2011-02-07
申请人： Toshihiko Saito , Takanori Matsuzaki , Shuhei Nagatsuka , Hiroki Inoue
发明人： Toshihiko Saito , Takanori Matsuzaki , Shuhei Nagatsuka , Hiroki Inoue
IPC分类号： G11C11/14
CPC分类号： G11C11/405 , H01L27/11521 , H01L27/1156 , H01L27/1225 , H01L28/40
摘要： A semiconductor device includes a first signal line, a second signal line, a memory cell, and a potential converter circuit. The memory cell includes a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region; and a capacitor. The first channel formation region and the second channel formation region include different semiconductor materials. The second drain electrode, one electrode of the capacitor, and the first gate electrode are electrically connected to one another. The second gate electrode is electrically connected to the potential converter circuit through the second signal line.
摘要翻译：半导体器件包括第一信号线，第二信号线，存储单元和电位转换器电路。存储单元包括：第一晶体管，包括第一栅极电极，第一源电极，第一漏极电极和第一沟道形成区域; 第二晶体管，包括第二栅极电极，第二源极电极，第二漏极电极和第二沟道形成区域; 和电容器。第一沟道形成区域和第二沟道形成区域包括不同的半导体材料。第二漏电极，电容器的一个电极和第一栅电极彼此电连接。第二栅极通过第二信号线电连接到电位转换器电路。

6. 发明授权

US08441868B2 Semiconductor memory having a read circuit 有权
标题翻译：具有读取电路的半导体存储器
公开(公告)号：US08441868B2
公开(公告)日：2013-05-14
申请号：US13078019
申请日：2011-04-01
申请人： Toshihiko Saito
发明人： Toshihiko Saito
IPC分类号： G11C7/00
CPC分类号： G11C16/06 , G11C16/26
摘要： The semiconductor device includes the read circuit which reads data written to a memory cell. The read circuit includes a first transistor, a second transistor, a first switch, and a second switch. A first terminal of the first transistor is electrically connected to a gate of the first transistor, and a second terminal of the first transistor is electrically connected to an output from the read circuit via the first switch. A first terminal of the second transistor is electrically connected to a gate of the second transistor, and a second terminal of the second transistor is electrically connected to the output from the read circuit via the second switch. A channel formation region of the first transistor can be formed using an oxide semiconductor, and a channel formation region of the second transistor can be formed using silicon.
摘要翻译：半导体器件包括读取写入存储单元的数据的读取电路。读取电路包括第一晶体管，第二晶体管，第一开关和第二开关。第一晶体管的第一端子电连接到第一晶体管的栅极，并且第一晶体管的第二端子经由第一开关电连接到来自读取电路的输出端。第二晶体管的第一端子电连接到第二晶体管的栅极，并且第二晶体管的第二端子经由第二开关电连接到来自读取电路的输出端。可以使用氧化物半导体形成第一晶体管的沟道形成区域，并且可以使用硅形成第二晶体管的沟道形成区域。

7. 发明授权

US08432718B2 Semiconductor memory device 有权
公开(公告)号：US08432718B2
公开(公告)日：2013-04-30
申请号：US12960117
申请日：2010-12-03
申请人： Toshihiko Saito
发明人： Toshihiko Saito
IPC分类号： G11C17/00
CPC分类号： H01L27/1225 , G11C17/12 , G11C17/18 , H01L27/105 , H01L27/1052 , H01L27/1214 , H01L27/1288
摘要： To provide a semiconductor memory device including an oxide semiconductor that can deal with instability of a threshold characteristic, in which writing is possible by a simple method. The semiconductor memory device functions by utilizing a characteristic that a threshold shifts when a thin film transistor including an oxide semiconductor is irradiated with ultraviolet light. Readout can be performed by setting a readout voltage between the threshold before the ultraviolet light irradiation and the threshold after irradiation. The threshold characteristic of an initial characteristic can be controlled by providing a back gate or by using two thin film transistors.

8. 发明申请

US20120261734A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120261734A1
公开(公告)日：2012-10-18
申请号：US13443027
申请日：2012-04-10
申请人： Toshihiko Saito
发明人： Toshihiko Saito
IPC分类号： H01L27/108
CPC分类号： H01L27/10805 , G11C11/405 , G11C16/0433 , H01L21/84 , H01L27/0288 , H01L27/1156 , H01L27/1203 , H01L27/1225 , H01L28/60 , H01L28/86 , H01L28/90
摘要： In the semiconductor memory device, one of a source and a drain of a first transistor is connected to one of a source and a drain of a second transistor, a gate of the first transistor is connected to one of a source and a drain of a third transistor and one of a pair of capacitor electrodes included in a capacitor, the other of the source and the drain of the first transistor and the other of the source and the drain of the third transistor are connected to a bit line, the other of the pair of capacitor electrodes included in the capacitor is connected to a common wiring, and the common wiring is grounded (GND). The common wiring has a net shape when seen from the above, and the third transistor is provided in a mesh formed by the common wiring.
摘要翻译：在半导体存储器件中，第一晶体管的源极和漏极之一连接到第二晶体管的源极和漏极之一，第一晶体管的栅极连接到源极和漏极之一第三晶体管和包括在电容器中的一对电容器电极中的一个，第一晶体管的源极和漏极中的另一个以及第三晶体管的源极和漏极中的另一个连接到位线，另一个包括在电容器中的一对电容器电极连接到公共布线，并且公共布线接地（GND）。当从上方观察时，公共布线具有净形状，并且第三晶体管设置在由公共布线形成的网格中。

9. 发明授权

US08264874B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08264874B2
公开(公告)日：2012-09-11
申请号：US12890856
申请日：2010-09-27
申请人： Toshihiko Saito , Takanori Matsuzaki
发明人： Toshihiko Saito , Takanori Matsuzaki
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C17/16 , G11C2213/33 , G11C2213/34 , G11C2213/79 , H01L27/24
摘要： Objects of the present invention are to improve the manufacturing yield of semiconductor devices, reduce manufacturing cost of the semiconductor device, and reduce the circuit area of an integrated circuit included in the semiconductor device. A memory layer of a memory element and a resistive layer of a resistor included in the semiconductor device are formed of the same material. Therefore, the memory layer and the resistive layer are formed in the same step, whereby the number of manufacturing steps of the semiconductor device can be reduced. As a result, the manufacturing yield of the semiconductor devices can be improved and the manufacturing cost can be reduced. In addition, the semiconductor device includes a resistor having a resistive component which has high resistance value. Consequently, the area of the integrated circuit included in the semiconductor device can be reduced.
摘要翻译：本发明的目的是提高半导体器件的制造成品率，降低半导体器件的制造成本，并且减小包括在半导体器件中的集成电路的电路面积。存储元件的存储层和包含在半导体器件中的电阻器的电阻层由相同的材料形成。因此，在相同的步骤中形成存储层和电阻层，从而可以减少半导体器件的制造步骤的数量。结果，可以提高半导体器件的制造成品率，并且可以降低制造成本。此外，半导体器件包括具有高电阻值的电阻元件的电阻器。因此，可以减少包括在半导体器件中的集成电路的面积。

10. 发明申请

US20120127781A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120127781A1
公开(公告)日：2012-05-24
申请号：US13298235
申请日：2011-11-16
申请人： Toshihiko Saito
发明人： Toshihiko Saito
IPC分类号： G11C11/24
CPC分类号： H01L27/1082 , G11C11/401 , G11C11/404 , G11C11/4096 , H01L21/84 , H01L27/108 , H01L27/1085 , H01L27/10852 , H01L27/10873 , H01L27/1203 , H01L28/40 , H01L28/60 , H01L29/7869
摘要： To increase a storage capacity of a memory module per unit area, and to provide a memory module with low power consumption, a transistor formed using an oxide semiconductor film, a silicon carbide film, a gallium nitride film, or the like, which is highly purified and has a wide band gap of 2.5 eV or higher is used for a DRAM, so that a retention period of potentials in a capacitor can be extended. Further, a memory cell has n capacitors with different capacitances and the n capacitors are each connected to a corresponding one of n data lines, so that a variety of the storage capacitances can be obtained and multilevel data can be stored. The capacitors may be stacked for reducing the area of the memory cell.
摘要翻译：为了增加每单位面积的存储器模块的存储容量，并且提供具有低功耗的存储器模块，使用高度的氧化物半导体膜，碳化硅膜，氮化镓膜等形成的晶体管纯化并且具有2.5eV或更高的宽带隙用于DRAM，使得可以延长电容器中的电位的保持期。此外，存储单元具有n个具有不同电容的电容器，并且n个电容器各自连接到n个数据线中的相应的一个，从而可以获得各种存储电容并且可以存储多级数据。电容器可以被堆叠以减小存储单元的面积。

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