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1. 发明授权

US09490324B2 N-polar III-nitride transistors 有权
公开(公告)号：US09490324B2
公开(公告)日：2016-11-08
申请号：US14744526
申请日：2015-06-19
申请人： Transphorm Inc.
发明人： Umesh Mishra , Srabanti Chowdhury , Carl Joseph Neufeld
IPC分类号： H01L29/66 , H01L29/10 , H01L29/205 , H01L29/78 , H01L29/778 , H01L29/20 , H01L29/04
CPC分类号： H01L29/1054 , H01L29/045 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7781 , H01L29/7785 , H01L29/78
摘要： An N-polar III-N transistor includes a III-N buffer layer, a first III-N barrier layer, and a III-N channel layer, the III-N channel layer having a gate region and a plurality of access regions on opposite sides of the gate region. The compositional difference between the first III-N barrier layer and the III-N channel layer causes a conductive channel to be induced in the access regions of the III-N channel layer. The transistor also includes a source, a gate, a drain, and a second III-N barrier layer between the gate and the III-N channel layer. The second III-N barrier layer has an N-face proximal to the gate and a group-III face opposite the N-face, and has a larger bandgap than the III-N channel layer. The lattice constant of the first III-N barrier layer is within 0.5% of the lattice constant of the buffer layer.

2. 发明申请

US20160064495A1 SEMICONDUCTOR DEVICES WITH INTEGRATED HOLE COLLECTORS 有权
标题翻译：具有集成孔收集器的半导体器件
公开(公告)号：US20160064495A1
公开(公告)日：2016-03-03
申请号：US14934565
申请日：2015-11-06
申请人： Transphorm Inc.
发明人： Umesh Mishra , Srabanti Chowdhury , Ilan Ben-Yaacov
IPC分类号： H01L29/40 , H01L29/20 , H01L29/207 , H01L29/78
CPC分类号： H01L29/402 , H01L29/0619 , H01L29/2003 , H01L29/207 , H01L29/42316 , H01L29/4236 , H01L29/42376 , H01L29/7786 , H01L29/78
摘要： Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons.
摘要翻译：描述了包括具有集成的空穴集电区域的半导体层的晶体管器件。空穴集电极区域被配置为在操作期间收集在晶体管器件中产生的空穴并且将它们远离器件的有源区域传送。空穴集电极区域可以电连接或耦合到器件的源极，漏极或场板。空穴集电极区域可以被掺杂，例如p型或名义上的p型，并且能够导通空穴而不是电子。

3. 发明申请

US20150333147A1 TRANSISTORS WITH ISOLATION REGIONS 有权
标题翻译：具有隔离区的晶体管
公开(公告)号：US20150333147A1
公开(公告)日：2015-11-19
申请号：US14810906
申请日：2015-07-28
申请人： Transphorm Inc.
发明人： Umesh Mishra , Srabanti Chowdhury
IPC分类号： H01L29/66 , H01L29/423 , H01L29/40 , H01L29/06 , H01L29/20
CPC分类号： H01L29/66462 , H01L29/0649 , H01L29/0657 , H01L29/2003 , H01L29/207 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/778 , H01L29/7786 , H01L2924/0002 , H01L2924/00
摘要： A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a plurality of channel access regions in the semiconductor material on either side of the gate, a channel in the semiconductor material having an effective width in the gate region and in the channel access regions, and an isolation region in the gate region. The isolation region serves to reduce the effective width of the channel in the gate region without substantially reducing the effective width of the channel in the access regions. Alternatively, the isolation region can be configured to collect holes that are generated in the transistor device. The isolation region may simultaneously achieve both of these functions.
摘要翻译：描述了一种晶体管器件，其包括源极，栅极，漏极，包括源极和漏极之间的栅极区域的半导体材料，栅极两侧的半导体材料中的多个沟道存取区域，沟道在栅极区域和沟道存取区域中具有有效宽度的半导体材料以及栅极区域中的隔离区域。隔离区域用于减小栅极区域中的沟道的有效宽度，而基本上不会减小通路区域中的通道的有效宽度。或者，隔离区域可以被配置为收集在晶体管器件中产生的空穴。隔离区域可以同时实现这两个功能。

4. 发明授权

US09171836B2 Method of forming electronic components with increased reliability 有权
标题翻译：形成电子元件的可靠性提高的方法
公开(公告)号：US09171836B2
公开(公告)日：2015-10-27
申请号：US14478504
申请日：2014-09-05
申请人： Transphorm Inc.
发明人： Rakesh K. Lal , Robert Coffie , Yifeng Wu , Primit Parikh , Yuvaraj Dora , Umesh Mishra , Srabanti Chowdhury , Nicholas Fichtenbaum
IPC分类号： H03K17/687 , H01L27/02 , H01L25/00 , H01L21/8236 , H01L27/06 , H01L49/02 , H01L29/778 , H03K17/10 , H01L29/423 , H01L29/872 , H01L29/20
CPC分类号： H01L27/0288 , H01L21/8236 , H01L25/00 , H01L27/0629 , H01L28/20 , H01L29/2003 , H01L29/42376 , H01L29/4238 , H01L29/7786 , H01L29/872 , H01L2924/0002 , H03K17/102 , H03K2017/6875 , Y10T29/49117 , H01L2924/00
摘要： An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.
摘要翻译：电子部件包括耗尽型晶体管，增强型晶体管和电阻。耗尽型晶体管具有比增强型晶体管更高的击穿电压。电阻器的第一端子电连接到增强型晶体管的源极，并且电阻器的第二端子和耗尽型晶体管的源极电连接到增强型晶体管的漏极。耗尽型晶体管的栅极可以电连接到增强型晶体管的源极。

5. 发明申请

US20150287785A1 N-POLAR III-NITRIDE TRANSISTORS 有权
标题翻译： N-极III型氮化物晶体管
公开(公告)号：US20150287785A1
公开(公告)日：2015-10-08
申请号：US14744526
申请日：2015-06-19
申请人： Transphorm Inc.
发明人： Umesh Mishra , Srabanti Chowdhury , Carl Joseph Neufeld
IPC分类号： H01L29/10 , H01L29/20 , H01L29/04 , H01L29/66
CPC分类号： H01L29/1054 , H01L29/045 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7781 , H01L29/7785 , H01L29/78
摘要： An N-polar III-N transistor includes a III-N buffer layer, a first III-N barrier layer, and a III-N channel layer, the III-N channel layer having a gate region and a plurality of access regions on opposite sides of the gate region. The compositional difference between the first III-N barrier layer and the III-N channel layer causes a conductive channel to be induced in the access regions of the III-N channel layer. The transistor also includes a source, a gate, a drain, and a second III-N barrier layer between the gate and the III-N channel layer. The second III-N barrier layer has an N-face proximal to the gate and a group-III face opposite the N-face, and has a larger bandgap than the III-N channel layer. The lattice constant of the first III-N barrier layer is within 0.5% of the lattice constant of the buffer layer.
摘要翻译： N极III-N晶体管包括III-N缓冲层，第一III-N势垒层和III-N沟道层，III-N沟道层具有栅极区域和相对的多个访问区域门区域两侧。第一III-N势垒层和III-N沟道层之间的组成差异导致在III-N沟道层的访问区域中引起导电沟道。晶体管还包括栅极和III-N沟道层之间的源极，栅极，漏极和第二III-N势垒层。第二III-N阻挡层具有靠近栅极的N面和与N面相对的III族面，并且具有比III-N沟道层更大的带隙。第一III-N势垒层的晶格常数在缓冲层的晶格常数的0.5％以内。

6. 发明授权

US09093366B2 N-polar III-nitride transistors 有权
标题翻译： N-极性III族氮化物晶体管
公开(公告)号：US09093366B2
公开(公告)日：2015-07-28
申请号：US13859635
申请日：2013-04-09
申请人： Transphorm Inc.
发明人： Umesh Mishra , Srabanti Chowdhury , Carl Joseph Neufeld
IPC分类号： H01L29/66 , H01L29/205 , H01L29/78 , H01L29/778 , H01L29/20
CPC分类号： H01L29/1054 , H01L29/045 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7781 , H01L29/7785 , H01L29/78
摘要： An N-polar III-N transistor includes a III-N buffer layer, a first III-N barrier layer, and a III-N channel layer, the III-N channel layer having a gate region and a plurality of access regions on opposite sides of the gate region. The compositional difference between the first III-N barrier layer and the III-N channel layer causes a conductive channel to be induced in the access regions of the III-N channel layer. The transistor also includes a source, a gate, a drain, and a second III-N barrier layer between the gate and the III-N channel layer. The second III-N barrier layer has an N-face proximal to the gate and a group-III face opposite the N-face, and has a larger bandgap than the III-N channel layer. The lattice constant of the first III-N barrier layer is within 0.5% of the lattice constant of the buffer layer.
摘要翻译： N极III-N晶体管包括III-N缓冲层，第一III-N势垒层和III-N沟道层，III-N沟道层具有栅极区域和相对的多个访问区域门区域两侧。第一III-N势垒层和III-N沟道层之间的组成差异导致在III-N沟道层的访问区域中引起导电沟道。晶体管还包括栅极和III-N沟道层之间的源极，栅极，漏极和第二III-N势垒层。第二III-N阻挡层具有靠近栅极的N面和与N面相对的III族面，并且具有比III-N沟道层更大的带隙。第一III-N势垒层的晶格常数在缓冲层的晶格常数的0.5％以内。

7. 发明申请

US20160043211A1 ELECTRODES FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME 有权
标题翻译：用于半导体器件的电极及其形成方法
公开(公告)号：US20160043211A1
公开(公告)日：2016-02-11
申请号：US14920059
申请日：2015-10-22
申请人： Transphorm Inc.
发明人： Srabanti Chowdhury , Umesh Mishra , Yuvaraj Dora
IPC分类号： H01L29/778 , H01L29/205 , H01L29/417 , H01L23/31 , H01L23/29 , H01L29/423 , H01L29/20 , H01L29/04
CPC分类号： H01L29/7787 , H01L21/28114 , H01L21/283 , H01L21/28581 , H01L21/28587 , H01L21/28593 , H01L21/76804 , H01L23/291 , H01L23/3171 , H01L29/045 , H01L29/0696 , H01L29/2003 , H01L29/205 , H01L29/402 , H01L29/41 , H01L29/41725 , H01L29/41766 , H01L29/42316 , H01L29/4236 , H01L29/42376 , H01L29/4238 , H01L29/66462 , H01L29/778 , H01L2924/0002 , H01L2924/00
摘要： A III-N semiconductor HEMT device includes an electrode-defining layer on a III-N material structure. The electrode-defining layer has a recess with a first sidewall proximal to the drain and a second sidewall proximal to the source, each sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a larger width than a portion of the recess proximal to the III-N material structure. An electrode is in the recess, the electrode including an extending portion over the first sidewall. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle.
摘要翻译： III-N半导体HEMT器件包括在III-N材料结构上的电极限定层。电极限定层具有凹槽，其具有靠近漏极的第一侧壁和靠近源极的第二侧壁，每个侧壁包括多个台阶。远离III-N材料结构的凹部的一部分具有比靠近III-N材料结构的凹部的一部分更大的宽度。电极在凹槽中，电极包括在第一侧壁上的延伸部分。电极限定层的一部分位于延伸部分和III-N材料结构之间。第一侧壁相对于III-N材料结构的表面形成第一有效角度，并且第二侧壁相对于III-N材料结构的表面形成第二有效角度，第二有效角度大于第一有效角度角度。

8. 发明授权

US09224805B2 Semiconductor devices with guard rings 有权
标题翻译：带保护环的半导体器件
公开(公告)号：US09224805B2
公开(公告)日：2015-12-29
申请号：US14530204
申请日：2014-10-31
申请人： Transphorm Inc.
发明人： Umesh Mishra , Srabanti Chowdhury , Yuvaraj Dora
IPC分类号： H01L29/02 , H01L29/06 , H01L29/40 , H01L29/66 , H01L29/778 , H01L29/872 , H01L21/76 , H01L29/417 , H01L29/423 , H01L29/20
CPC分类号： H01L29/0623 , H01L21/76 , H01L29/0619 , H01L29/2003 , H01L29/402 , H01L29/404 , H01L29/41766 , H01L29/42376 , H01L29/66212 , H01L29/66462 , H01L29/7786 , H01L29/872
摘要： Semiconductor devices with guard rings are described. The semiconductor devices may be, e.g., transistors and diodes designed for high-voltage applications. A guard ring is a floating electrode formed of electrically conducting material above a semiconductor material layer. A portion of an insulating layer is between at least a portion of the guard ring and the semiconductor material layer. A guard ring may be located, for example, on a transistor between a gate and a drain electrode. A semiconductor device may have one or more guard rings.
摘要翻译：描述具有保护环的半导体器件。半导体器件可以是例如设计用于高电压应用的晶体管和二极管。保护环是由半导体材料层上方的导电材料形成的浮动电极。绝缘层的一部分位于保护环和半导体材料层的至少一部分之间。保护环可以位于例如栅极和漏极之间的晶体管上。半导体器件可以具有一个或多个保护环。

9. 发明授权

US09171910B2 Semiconductor electronic components with integrated current limiters 有权
标题翻译：具有集成限流器的半导体电子元件
公开(公告)号：US09171910B2
公开(公告)日：2015-10-27
申请号：US14311600
申请日：2014-06-23
申请人： Transphorm Inc.
发明人： Yifeng Wu , Umesh Mishra , Srabanti Chowdhury
IPC分类号： H01L27/12 , H01L29/20 , H01L29/778 , H01L27/06 , H01L27/088
CPC分类号： H01L27/0883 , H01L27/0605 , H01L29/16 , H01L29/2003 , H01L29/778 , H03K17/687
摘要： An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor.
摘要翻译：电子部件包括高电压耗尽型晶体管和低电压增强型晶体管。高电压耗尽型晶体管的源电极电连接到低电压增强型晶体管的漏电极，高电压耗尽型晶体管的栅电极电耦合到低电压增强型晶体管。增强型晶体管的导通电阻小于耗尽型晶体管的导通电阻，并且增强型晶体管的最大电流电平小于耗尽型晶体管的最大电流电平。

10. 发明授权

US09171730B2 Electrodes for semiconductor devices and methods of forming the same 有权
标题翻译：用于半导体器件的电极及其形成方法
公开(公告)号：US09171730B2
公开(公告)日：2015-10-27
申请号：US14179788
申请日：2014-02-13
申请人： Transphorm Inc.
发明人： Srabanti Chowdhury , Umesh Mishra , Yuvaraj Dora
IPC分类号： H01L21/338 , H01L21/283 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/778 , H01L21/28 , H01L21/768 , H01L21/285 , H01L29/417 , H01L29/04 , H01L29/06 , H01L29/20
CPC分类号： H01L29/7787 , H01L21/28114 , H01L21/283 , H01L21/28581 , H01L21/28587 , H01L21/28593 , H01L21/76804 , H01L23/291 , H01L23/3171 , H01L29/045 , H01L29/0696 , H01L29/2003 , H01L29/205 , H01L29/402 , H01L29/41 , H01L29/41725 , H01L29/41766 , H01L29/42316 , H01L29/4236 , H01L29/42376 , H01L29/4238 , H01L29/66462 , H01L29/778 , H01L2924/0002 , H01L2924/00
摘要： A III-N semiconductor HEMT device includes an electrode-defining layer on a III-N material structure. The electrode-defining layer has a recess with a first sidewall proximal to the drain and a second sidewall proximal to the source, each sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a larger width than a portion of the recess proximal to the III-N material structure. An electrode is in the recess, the electrode including an extending portion over the first sidewall. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle.
摘要翻译： III-N半导体HEMT器件包括在III-N材料结构上的电极限定层。电极限定层具有凹槽，其具有靠近漏极的第一侧壁和靠近源极的第二侧壁，每个侧壁包括多个台阶。远离III-N材料结构的凹部的一部分具有比靠近III-N材料结构的凹部的一部分更大的宽度。电极在凹槽中，电极包括在第一侧壁上的延伸部分。电极限定层的一部分位于延伸部分和III-N材料结构之间。第一侧壁相对于III-N材料结构的表面形成第一有效角度，并且第二侧壁相对于III-N材料结构的表面形成第二有效角度，第二有效角度大于第一有效角度角度。

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