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1. 发明授权

US08173990B2 Memory array with a selector connected to multiple resistive cells 有权
标题翻译：具有选择器的存储器阵列连接到多个电阻单元
公开(公告)号：US08173990B2
公开(公告)日：2012-05-08
申请号：US12691549
申请日：2010-01-21
申请人： Tzyh-Cheang Lee , Chun-Sheng Liang , Jiunn-Ren Hwang , Fu-Liang Yang
发明人： Tzyh-Cheang Lee , Chun-Sheng Liang , Jiunn-Ren Hwang , Fu-Liang Yang
IPC分类号： H01L45/00
CPC分类号： H01L27/2436 , G11C13/0004 , G11C13/003 , G11C2213/78 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要： An array includes a transistor comprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug.
摘要翻译：阵列包括：晶体管，包括第一端子，第二端子和第三端子; 连接到所述晶体管的第一端子的第一接触插塞; 连接到晶体管的第一端子的第二接触插塞; 第一电阻式存储单元，具有第一端和第二端，其中所述第一端连接到所述第一接触插塞; 以及具有第三端和第四端的第二电阻式存储单元，其中所述第三端连接到所述第二接触插塞。

2. 发明授权

US07663134B2 Memory array with a selector connected to multiple resistive cells 失效
标题翻译：具有选择器的存储器阵列连接到多个电阻单元
公开(公告)号：US07663134B2
公开(公告)日：2010-02-16
申请号：US11775741
申请日：2007-07-10
申请人： Tzyh-Cheang Lee , Chun-Sheng Liang , Jiunn-Ren Hwang , Fu-Liang Yang
发明人： Tzyh-Cheang Lee , Chun-Sheng Liang , Jiunn-Ren Hwang , Fu-Liang Yang
IPC分类号： H01L47/00
CPC分类号： H01L27/2436 , G11C13/0004 , G11C13/003 , G11C2213/78 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要： An array includes a transistor cpmprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug.
摘要翻译：阵列包括：晶体管，包括第一端子，第二端子和第三端子; 连接到所述晶体管的第一端子的第一接触插塞; 连接到晶体管的第一端子的第二接触插塞; 第一电阻式存储单元，具有第一端和第二端，其中所述第一端连接到所述第一接触插塞; 以及具有第三端和第四端的第二电阻式存储单元，其中所述第三端连接到所述第二接触插塞。

3. 发明申请

US20100117045A1 Memory Array with a Selector Connected to Multiple Resistive Cells 有权
标题翻译：具有连接到多个电阻单元的选择器的存储器阵列
公开(公告)号：US20100117045A1
公开(公告)日：2010-05-13
申请号：US12691549
申请日：2010-01-21
申请人： Tzyh-Cheang Lee , Chun-Sheng Liang , Jiunn-Ren Hwang , Fu-Liang Yang
发明人： Tzyh-Cheang Lee , Chun-Sheng Liang , Jiunn-Ren Hwang , Fu-Liang Yang
IPC分类号： H01L47/00
CPC分类号： H01L27/2436 , G11C13/0004 , G11C13/003 , G11C2213/78 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要： An array includes a transistor comprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug.
摘要翻译：阵列包括：晶体管，包括第一端子，第二端子和第三端子; 连接到所述晶体管的第一端子的第一接触插塞; 连接到晶体管的第一端子的第二接触插塞; 第一电阻式存储单元，具有第一端和第二端，其中所述第一端连接到所述第一接触插塞; 以及具有第三端和第四端的第二电阻式存储单元，其中所述第三端连接到所述第二接触插塞。

4. 发明申请

US20090014836A1 Memory Array with a Selector Connected to Multiple Resistive Cells 失效
标题翻译：具有连接到多个电阻单元的选择器的存储器阵列
公开(公告)号：US20090014836A1
公开(公告)日：2009-01-15
申请号：US11775741
申请日：2007-07-10
申请人： Tzyh-Cheang Lee , Chun-Sheng Liang , Jiunn-Ren Hwang , Fu-Liang Yang
发明人： Tzyh-Cheang Lee , Chun-Sheng Liang , Jiunn-Ren Hwang , Fu-Liang Yang
IPC分类号： G11C11/00 , H01L29/00
CPC分类号： H01L27/2436 , G11C13/0004 , G11C13/003 , G11C2213/78 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要： An array includes a transistor comprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug.
摘要翻译：阵列包括：晶体管，包括第一端子，第二端子和第三端子; 连接到所述晶体管的第一端子的第一接触插塞; 连接到晶体管的第一端子的第二接触插塞; 第一电阻式存储单元，具有第一端和第二端，其中所述第一端连接到所述第一接触插塞; 以及具有第三端和第四端的第二电阻式存储单元，其中所述第三端连接到所述第二接触插塞。

5. 发明授权

US07482231B2 Manufacturing of memory array and periphery 有权
标题翻译：内存阵列和周边的制造
公开(公告)号：US07482231B2
公开(公告)日：2009-01-27
申请号：US11529067
申请日：2006-09-28
申请人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
发明人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
IPC分类号： H01L21/8239
CPC分类号： H01L29/4983 , H01L21/28282 , H01L21/823828 , H01L21/823864 , H01L27/1052 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： Method of manufacturing a semiconductor chip. An array region gate stack is formed on an array region of a substrate and a periphery region gate stack is formed on a periphery region of a substrate. A first dielectric material, a charge-storing material, and a second dielectric material are deposited over the substrate. Portions of the first dielectric material, the charge-storing material, and the second dielectric material are removed to form storage structures on the array region gate stack and on the periphery region gate stack. The storage structures have a generally L-shaped cross-section. A first source/drain region is formed in the array region well. A third dielectric material and a spacer material are deposited over the substrate. Portions of the third dielectric material and the spacer material are removed to form spacers. A second source/drain region is formed in the periphery region well.
摘要翻译：制造半导体芯片的方法在基板的阵列区域上形成阵列区域栅极叠层，并且在基板的周边区域上形成周边区域栅叠层。在衬底上沉积第一介电材料，电荷存储材料和第二介电材料。去除第一介电材料的部分，电荷存储材料和第二介电材料，以在阵列区域栅极叠层和周边区域栅叠层上形成存储结构。存储结构具有大致L形的横截面。在阵列区域中形成第一源极/漏极区域。在衬底上沉积第三介电材料和间隔物材料。去除第三电介质材料和间隔物材料的部分以形成间隔物。在周边区域中形成第二源极/漏极区域。

6. 发明授权

US07482236B2 Structure and method for a sidewall SONOS memory device 有权
标题翻译：侧壁SONOS存储器件的结构和方法
公开(公告)号：US07482236B2
公开(公告)日：2009-01-27
申请号：US11602809
申请日：2006-11-21
申请人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
发明人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
IPC分类号： H01L21/8234
CPC分类号： H01L29/4983 , H01L21/28282 , H01L21/823828 , H01L21/823864 , H01L27/1052 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/792 , H01L29/7923 , Y10S438/954
摘要： A gate stack is formed on a substrate. The gate stack has a sidewall. An oxide-nitride-oxide material is deposited on the gate stack. Portions of the oxide-nitride-oxide material are removed to form an oxide-nitride-oxide structure. The oxide-nitride-oxide structure has a generally L-shaped cross-section with a vertical portion along at least part of the gate stack sidewall and a horizontal portion along the substrate. A top oxide material is deposited over the substrate. A silicon nitride spacer material is deposited over the top oxide material. Portions of the top oxide material and the silicon nitride spacer material are removed to form a silicon nitride spacer separated from the oxide-nitride-oxide stack by the top oxide material. Source/drain regions are formed in the substrate.
摘要翻译：栅极堆叠形成在基板上。栅极堆叠具有侧壁。氧化物 - 氮化物 - 氧化物材料沉积在栅极叠层上。除去氧化物 - 氮化物 - 氧化物材料的一部分以形成氧化物 - 氧化物 - 氧化物结构。氧化物 - 氧化物 - 氧化物结构具有通常为L形的横截面，沿着栅极叠层侧壁的至少一部分和沿着衬底的水平部分具有垂直部分。顶部氧化物材料沉积在衬底上。在顶部氧化物材料上沉积氮化硅间隔物材料。除去顶部氧化物材料和氮化硅间隔物材料的部分以形成通过顶部氧化物材料从氧化物 - 氮化物 - 氧化物堆叠体分离的氮化硅间隔物。源极/漏极区域形成在衬底中。

7. 发明申请

US20070145465A1 Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof 有权
标题翻译：具有多晶硅存储点的非易失性浮动栅极存储单元及其制造方法
公开(公告)号：US20070145465A1
公开(公告)日：2007-06-28
申请号：US11313790
申请日：2005-12-22
申请人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
发明人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
IPC分类号： H01L29/788
CPC分类号： H01L29/42332 , H01L21/28273 , H01L29/7881
摘要： Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof. The non-volatile floating gate memory cell comprises a semiconductor substrate of a first conductivity type. A first region of a second conductivity type different from the first conductivity type is formed in the semiconductor substrate. A second region of the second conductivity type is formed in the semiconductor substrate spaced apart from the first region. A channel region connects the first and second regions for the conduction of charges. A dielectric layer is disposed on the channel region. A control gate is disposed on the dielectric layer. A tunnel dielectric layer is conformably formed on the semiconductor substrate and the control gate. Two charge storage dots are spaced apart from each other at opposing lateral edges of the sidewalls of the control gate and surface of the semiconductor substrate.
摘要翻译：具有多晶硅存储点的非易失性浮动栅极存储单元及其制造方法。非易失性浮动栅极存储单元包括第一导电类型的半导体衬底。在半导体衬底中形成不同于第一导电类型的第二导电类型的第一区域。第二导电类型的第二区域形成在与第一区域间隔开的半导体衬底中。通道区域连接第一和第二区域用于电荷传导。电介质层设置在沟道区上。控制栅极设置在电介质层上。在半导体衬底和控制栅上一致地形成隧道介电层。两个电荷存储点在控制栅极的侧壁和半导体衬底的表面的相对侧边缘处彼此间隔开。

8. 发明申请

US20070096200A1 Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory 审中-公开
标题翻译：用于高速随机存取存储器侧壁控制栅极的自对准导电间隔物工艺
公开(公告)号：US20070096200A1
公开(公告)日：2007-05-03
申请号：US11642658
申请日：2006-12-21
申请人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
发明人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/2815 , H01L29/40114 , H01L29/42324
摘要： A self-aligned conductive spacer process for fabricating sidewall control gates on both sides of a floating gate for high-speed RAM applications, which can well define dimensions and profiles of the sidewall control gates. A conductive layer is formed on the dielectric layer to cover a floating gate patterned on a semiconductor substrate. Oxide spacer are formed on the conductive layer adjacent to the sidewalls of the floating gate. Performing an anisotropic etch process on the conductive layer and using the oxide spacers as a hard mask, a conductive spacers are self-aligned fabricated at both sides of the floating gate, serving as sidewall control gates.
摘要翻译：一种用于在用于高速RAM应用的浮动栅极的两侧上制造侧壁控制栅极的自对准导电间隔物工艺，其可以很好地限定侧壁控制栅极的尺寸和轮廓。在电介质层上形成导电层，以覆盖图案化在半导体衬底上的浮动栅极。在与浮动栅极的侧壁相邻的导电层上形成氧化物间隔物。在导电层上进行各向异性蚀刻处理并使用氧化物间隔物作为硬掩模，导电间隔物在浮栅的两侧制造，用作侧壁控制栅极。

9. 发明授权

US07176084B2 Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory 有权
公开(公告)号：US07176084B2
公开(公告)日：2007-02-13
申请号：US11148342
申请日：2005-06-09
申请人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
发明人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/4763 , H01L21/3205 , H01L21/461 , H01L21/302
CPC分类号： H01L29/7881 , H01L21/2815 , H01L21/28273 , H01L29/42324
摘要： A self-aligned conductive spacer process for fabricating sidewall control gates on both sides of a floating gate for high-speed RAM applications, which can well define dimensions and profiles of the sidewall control gates. A conductive layer is formed on the dielectric layer to cover a floating gate patterned on a semiconductor substrate. Oxide spacer are formed on the conductive layer adjacent to the sidewalls of the floating gate. Performing an anisotropic etch process on the conductive layer and using the oxide spacers as a hard mask, a conductive spacers are self-aligned fabricated at both sides of the floating gate, serving as sidewall control gates.

10. 发明授权

US07355236B2 Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof 有权
标题翻译：具有多晶硅存储点的非易失性浮动栅极存储单元及其制造方法
公开(公告)号：US07355236B2
公开(公告)日：2008-04-08
申请号：US11313790
申请日：2005-12-22
申请人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
发明人： Tzyh-Cheang Lee , Fu-Liang Yang , Jiunn-Ren Hwang , Tsung-Lin Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/42332 , H01L21/28273 , H01L29/7881
摘要： Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof. The non-volatile floating gate memory cell comprises a semiconductor substrate of a first conductivity type. A first region of a second conductivity type different from the first conductivity type is formed in the semiconductor substrate. A second region of the second conductivity type is formed in the semiconductor substrate spaced apart from the first region. A channel region connects the first and second regions for the conduction of charges. A dielectric layer is disposed on the channel region. A control gate is disposed on the dielectric layer. A tunnel dielectric layer is conformably formed on the semiconductor substrate and the control gate. Two charge storage dots are spaced apart from each other at opposing lateral edges of the sidewalls of the control gate and surface of the semiconductor substrate.
摘要翻译：具有多晶硅存储点的非易失性浮动栅极存储单元及其制造方法。非易失性浮动栅极存储单元包括第一导电类型的半导体衬底。在半导体衬底中形成不同于第一导电类型的第二导电类型的第一区域。第二导电类型的第二区域形成在与第一区域间隔开的半导体衬底中。通道区域连接第一和第二区域用于电荷传导。电介质层设置在沟道区上。控制栅极设置在电介质层上。在半导体衬底和控制栅上一致地形成隧道介电层。两个电荷存储点在控制栅极的侧壁和半导体衬底的表面的相对侧边缘处彼此间隔开。

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