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1. 发明授权

US11088285B2 Oxide semiconductor field effect transistor and forming method thereof 有权
公开(公告)号：US11088285B2
公开(公告)日：2021-08-10
申请号：US16154644
申请日：2018-10-08
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chien-Ming Lai , Yen-Chen Chen , Jen-Po Huang , Sheng-Yao Huang , Hui-Ling Chen , Qinggang Xing , Ding-Lung Chen , Li Li Ding , Yao-Hung Liu
IPC分类号： H01L29/76 , H01L29/786 , H01L29/66 , H01L29/51 , H01L29/423 , H01L29/49 , H01L29/10
摘要： An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

2. 发明授权

US10446689B1 Manufacturing method of oxide semiconductor device 有权
公开(公告)号：US10446689B1
公开(公告)日：2019-10-15
申请号：US16274190
申请日：2019-02-12
申请人： UNITED MICROELECTRONICS CORP.
发明人： Jen-Po Huang , Chien-Ming Lai , Yen-Chen Chen , Sheng-Yao Huang , Hui-Ling Chen , Seng Wah Liau , Han Chuan Fang
IPC分类号： H01L29/768 , H01L29/417 , H01L29/66 , H01L21/4757 , H01L29/786
摘要： An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.

3. 发明授权

US10446688B1 Oxide semiconductor device and manufacturing method thereof 有权
公开(公告)号：US10446688B1
公开(公告)日：2019-10-15
申请号：US16190090
申请日：2018-11-13
申请人： UNITED MICROELECTRONICS CORP.
发明人： Jen-Po Huang , Chien-Ming Lai , Yen-Chen Chen , Sheng-Yao Huang , Hui-Ling Chen , Seng Wah Liau , Han Chuan Fang
IPC分类号： H01L29/786 , H01L29/417 , H01L21/4757 , H01L29/66
摘要： An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.

4. 发明申请

US20160093616A1 COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：补充金属氧化物半导体器件及其形成方法
公开(公告)号：US20160093616A1
公开(公告)日：2016-03-31
申请号：US14526552
申请日：2014-10-29
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chien-Ming Lai , Chien-Chung Huang , Yu-Ting Tseng , Ya-Huei Tsai , Yu-Ping Wang
IPC分类号： H01L27/092 , H01L29/49 , H01L21/28 , H01L21/8238
CPC分类号： H01L21/823437 , H01L21/28088 , H01L21/283 , H01L21/3211 , H01L21/32139 , H01L21/823842 , H01L27/092 , H01L27/0922 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.
摘要翻译：本发明提供一种互补金属氧化物半导体器件，其包括PMOS和NMOS。 PMOS具有P型金属栅极，其包括底部阻挡层，P功函数金属（PWFM）层，N功函数调整（NWFT）层，N功函数金属（NWFM）层和金属层。 NMOS具有N型金属栅极，其包括NWFT层，NWFM层和低电阻层。本发明还提供一种形成该方法的方法。

5. 发明授权

US09129985B2 Semiconductor device having metal gate and manufacturing method thereof 有权
标题翻译：具有金属栅极的半导体器件及其制造方法
公开(公告)号：US09129985B2
公开(公告)日：2015-09-08
申请号：US13784839
申请日：2013-03-05
申请人： UNITED MICROELECTRONICS CORP.
发明人： Po-Chao Tsao , Chien-Ting Lin , Chien-Ming Lai , Chi-Mao Hsu
IPC分类号： H01L29/76 , H01L29/94 , H01L29/66 , H01L29/49 , H01L29/51 , H01L29/78 , H01L21/8238
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/28185 , H01L21/32115 , H01L21/823842 , H01L27/0922 , H01L29/42364 , H01L29/42376 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/78 , H01L29/7833
摘要： A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench.
摘要翻译：具有金属栅极的半导体器件的制造方法包括以下步骤。提供了具有形成在其上的第一半导体器件和第二半导体器件的衬底。第一半导体器件包括第一栅极沟槽，第二半导体器件包括第二栅极沟槽。在第一栅极沟槽和第二栅极沟槽中形成第一功函数金属层。第一功函数金属层的一部分从第二栅极沟槽去除。在第一栅极沟槽和第二栅极沟槽中形成第二功函数金属层。第二功函数金属层和第一功函数金属层包括相同的金属材料。在第一栅极沟槽和第二栅极沟槽中依次形成第三功函数金属层和间隙填充金属层。

6. 发明申请

US20140252423A1 SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有金属门的半导体器件及其制造方法
公开(公告)号：US20140252423A1
公开(公告)日：2014-09-11
申请号：US13784839
申请日：2013-03-05
申请人： UNITED MICROELECTRONICS CORP.
发明人： Po-Chao Tsao , Chien-Ting Lin , Chien-Ming Lai , Chi-Mao Hsu
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/28185 , H01L21/32115 , H01L21/823842 , H01L27/0922 , H01L29/42364 , H01L29/42376 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/78 , H01L29/7833
摘要： A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench.
摘要翻译：具有金属栅极的半导体器件的制造方法包括以下步骤。提供了具有形成在其上的第一半导体器件和第二半导体器件的衬底。第一半导体器件包括第一栅极沟槽，第二半导体器件包括第二栅极沟槽。第一功函数金属层形成在第一栅极沟槽和第二栅极沟槽中。第一功函数金属层的一部分从第二栅极沟槽去除。在第一栅极沟槽和第二栅极沟槽中形成第二功函数金属层。第二功函数金属层和第一功函数金属层包括相同的金属材料。在第一栅极沟槽和第二栅极沟槽中依次形成第三功函数金属层和间隙填充金属层。

7. 发明申请

US20220399295A1 SEMICONDUCTOR STRUCTURE FOR WAFER LEVEL BONDING AND BONDED SEMICONDUCTOR STRUCTURE 有权
公开(公告)号：US20220399295A1
公开(公告)日：2022-12-15
申请号：US17382325
申请日：2021-07-21
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chien-Ming Lai
IPC分类号： H01L23/00
摘要： A semiconductor structure for wafer level bonding includes a bonding dielectric layer disposed on a substrate and a bonding pad disposed in the bonding dielectric layer. The bonding pad includes a top surface exposed from the bonding dielectric layer, a bottom surface opposite to the top surface, and a sidewall between the top surface and the bottom surface. A bottom angle between the bottom surface and sidewall of the bonding pad is smaller than 90 degrees.

8. 发明申请

US20210336059A1 OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR 有权
公开(公告)号：US20210336059A1
公开(公告)日：2021-10-28
申请号：US17367637
申请日：2021-07-06
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chien-Ming Lai , Yen-Chen Chen , Jen-Po Huang , Sheng-Yao Huang , Hui-Ling Chen , Qinggang Xing , Ding-Lung Chen , Li Li Ding , Yao-Hung Liu
IPC分类号： H01L29/786 , H01L29/66 , H01L29/51 , H01L29/423 , H01L29/49 , H01L29/10
摘要： An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

9. 发明授权

US09679898B2 Semiconductor device having metal gate 有权
公开(公告)号：US09679898B2
公开(公告)日：2017-06-13
申请号：US15339945
申请日：2016-11-01
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chien-Ming Lai , Ya-Huei Tsai
IPC分类号： H01L21/00 , H01L27/092 , H01L21/8238 , H01L21/28 , H01L21/3213 , H01L29/49 , H01L29/66 , H01L29/51
CPC分类号： H01L27/092 , H01L21/28088 , H01L21/32134 , H01L21/82345 , H01L21/8238 , H01L21/823842 , H01L27/0922 , H01L29/49 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor device having metal gate includes a first metal gate structure and a second metal gate structure disposed in a first device region and in a second device region on a substrate respectively. The first metal gate structure includes a gate insulating layer, a first bottom barrier layer, a top barrier layer, and a metal layer disposed on the substrate in order, wherein the top barrier layer is directly in contact with the first bottom barrier layer. The second metal gate structure includes the gate insulating layer, a second bottom barrier layer, the top barrier layer, and the metal layer on the substrate in order, wherein the top barrier layer is directly in contact with the second bottom barrier layer. The first bottom barrier layer and the second bottom barrier layer have different impurity compositions.

10. 发明授权

US09524967B1 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US09524967B1
公开(公告)日：2016-12-20
申请号：US15046458
申请日：2016-02-18
申请人： UNITED MICROELECTRONICS CORP.
发明人： Hao-Yeh Liu , Chien-Ming Lai , Yu-Ping Wang , Mon-Sen Lin , Ya-Huei Tsai , Ching-Hsiang Chiu
IPC分类号： H01L27/088 , H01L27/092 , H01L21/8234
CPC分类号： H01L27/088 , H01L21/82345 , H01L21/823842 , H01L27/092
摘要： A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first transistor, a second transistor and a third transistor all disposed on the substrate. The first transistor includes a first channel, and a first barrier layer and a first work function layer stacked with each other on the first channel. The second transistor includes a second channel, and a second barrier layer and a second work function layer stacked with each other. The third transistor includes a third channel and a third barrier layer and a third work function layer stacked with each other on the third channel, wherein the first barrier layer, the second barrier layer and the third barrier layer have different nitrogen ratio. The first, the second and the third transistors have different threshold voltages, respectively.
摘要翻译：半导体器件及其形成方法，所述半导体器件包括基板，以及全部设置在所述基板上的第一晶体管，第二晶体管和第三晶体管。第一晶体管包括第一通道，以及在第一通道上彼此堆叠的第一势垒层和第一功函数层。第二晶体管包括第二通道，以及彼此堆叠的第二阻挡层和第二功能层。第三晶体管包括在第三沟道上彼此堆叠的第三沟道和第三势垒层和第三功函数层，其中第一势垒层，第二阻挡层和第三势垒层具有不同的氮比。第一，第二和第三晶体管分别具有不同的阈值电压。

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