专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09385193B2 FINFET transistor structure and method for making the same 有权
标题翻译： FINFET晶体管结构及其制造方法
公开(公告)号：US09385193B2
公开(公告)日：2016-07-05
申请号：US14288369
申请日：2014-05-27
申请人： UNITED MICROELECTRONICS CORP.
发明人： Rai-Min Huang , Sheng-Huei Dai , Chen-Hua Tsai , Duan Quan Liao , Yikun Chen , Xiao Zhong Zhu
IPC分类号： H01L29/06 , H01L27/108 , H01L29/66 , H01L29/78
CPC分类号： H01L29/0653 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/785 , H01L29/7854
摘要： A FINFET transistor structure includes a substrate including a fin structure. Two combined recesses embedded within the substrate, wherein each of the combined recesses includes a first recess extending in a vertical direction and a second recess extending in a lateral direction, the second recess has a protruding side extending to and under the fin structure. Two filling layers respectively fill in the combined recesses. A gate structure crosses the fin structure.
摘要翻译： FINFET晶体管结构包括包括鳍结构的衬底。嵌入在基板内的两个组合的凹槽，其中每个组合的凹槽包括沿垂直方向延伸的第一凹部和沿横向方向延伸的第二凹槽，第二凹部具有延伸到翅片结构下方和下方的突出侧。两个填充层分别填充组合的凹部。栅极结构穿过鳍结构。

2. 发明申请

US20140225197A1 FINFET TRANSISTOR STRUCTURE AND METHOD FOR MAKING THE SAME 审中-公开
标题翻译： FINFET晶体管结构及其制造方法
公开(公告)号：US20140225197A1
公开(公告)日：2014-08-14
申请号：US14261441
申请日：2014-04-25
申请人： UNITED MICROELECTRONICS CORP.
发明人： Rai-Min Huang , Sheng-Huei Dai , Chen-Hua Tsai , Duan Quan Liao , Yikun Chen , Xiao Zhong Zhu
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/0653 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/785 , H01L29/7854
摘要： A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.
摘要翻译： FINFET晶体管结构包括衬底，鳍结构，绝缘层和栅极结构。翅片结构设置在基板上并直接连接到基板。此外，翅片结构包括翅片导电层和瓶颈。绝缘层覆盖基板，并且具有通过部分地围绕翅片结构的瓶颈而形成的突出侧，以及与基板直接接触的底侧，使得突出侧延伸到翅片结构的下方。门结构部分地围绕翅片结构。

3. 发明申请

US20150348789A1 SEMICONDUCTOR PROCESS 有权
标题翻译：半导体工艺
公开(公告)号：US20150348789A1
公开(公告)日：2015-12-03
申请号：US14288399
申请日：2014-05-28
申请人： UNITED MICROELECTRONICS CORP.
发明人： Duan Quan Liao , Wei Cheng , Yikun Chen , CHING HWA TEY , Xiao Zhong Zhu
IPC分类号： H01L21/28
CPC分类号： H01L21/28273 , H01L27/11521 , H01L27/11534
摘要： A semiconductor process includes the following steps. A first gate is formed on a substrate, wherein the first gate includes a stacked gate on the substrate and a cap on the stacked gate. A spacer material is formed to conformally cover the first gate and the substrate. The spacer material is etched to form a spacer on a side of the first gate and a block on the other side of the first gate corresponding to the side. A material covers the substrate, the block, the first gate and the spacer, wherein the top surface of the material is a flat surface. The block, the spacer and the material are pulled down with the same pulling selectivity so that an assisting gate is formed from the block and a selective gate is formed from the spacer.
摘要翻译：半导体工艺包括以下步骤。第一栅极形成在衬底上，其中第一栅极包括衬底上的堆叠栅极和堆叠栅极上的帽。形成间隔物材料以保形地覆盖第一栅极和衬底。蚀刻间隔材料以在第一栅极的一侧上形成间隔物，并且在第一栅极的另一侧上对应于侧面的块。材料覆盖基板，块，第一栅极和间隔件，其中材料的顶表面是平坦的表面。块，间隔物和材料以相同的拉拔选择性被拉下，使得从块形成辅助栅极，并且由间隔物形成选择栅极。

4. 发明授权

US09276057B2 Capacitor structure and method of manufacturing the same 有权
标题翻译：电容器结构及其制造方法
公开(公告)号：US09276057B2
公开(公告)日：2016-03-01
申请号：US14165535
申请日：2014-01-27
申请人： UNITED MICROELECTRONICS CORP.
发明人： Duan Quan Liao , Yikun Chen , Ching Hwa Tey , Xiao Zhong Zhu
IPC分类号： H01L29/94 , H01L49/02 , H01L21/768 , H01L23/522 , H01L23/532 , H01L27/108
CPC分类号： H01L28/75 , H01L21/76807 , H01L23/5223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L27/10808 , H01L27/10852 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure includes a substrate with a plurality of dielectric layers sequentially formed thereon, a trench formed in the dielectric layers, wherein the trench is composed of at least two interconnected dual damascene recesses, each dual damascene recess formed in one dielectric layer; and a capacitor multilayer disposed on the sidewall of the trench.
摘要翻译：电容器结构包括其上顺序地形成有多个电介质层的衬底，形成在电介质层中的沟槽，其中沟槽由至少两个互连的双镶嵌凹部组成，每个双镶嵌凹部形成在一个介电层中; 以及设置在沟槽的侧壁上的电容器多层。

5. 发明申请

US20150214293A1 CAPACITOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：电容器结构及其制造方法
公开(公告)号：US20150214293A1
公开(公告)日：2015-07-30
申请号：US14165535
申请日：2014-01-27
申请人： UNITED MICROELECTRONICS CORP.
发明人： Duan Quan Liao , Yikun Chen , CHING HWA TEY , Xiao Zhong Zhu
IPC分类号： H01L49/02 , H01L27/108
CPC分类号： H01L28/75 , H01L21/76807 , H01L23/5223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L27/10808 , H01L27/10852 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure includes a substrate with a plurality of dielectric layers sequentially formed thereon, a trench formed in the dielectric layers, wherein the trench is composed of at least two interconnected dual damascene recesses, each dual damascene recess formed in one dielectric layer; and a capacitor multilayer disposed on the sidewall of the trench.
摘要翻译：电容器结构包括其上顺序地形成有多个电介质层的衬底，形成在电介质层中的沟槽，其中沟槽由至少两个互连的双镶嵌凹部组成，每个双镶嵌凹部形成在一个介电层中; 以及设置在沟槽的侧壁上的电容器多层。

6. 发明申请

US20140252482A1 FINFET TRANSISTOR STRUCTURE AND METHOD FOR MAKING THE SAME 有权
标题翻译： FINFET晶体管结构及其制造方法
公开(公告)号：US20140252482A1
公开(公告)日：2014-09-11
申请号：US14288369
申请日：2014-05-27
申请人： UNITED MICROELECTRONICS CORP.
发明人： Rai-Min Huang , Sheng-Huei Dai , Chen-Hua Tsai , Duan Quan Liao , Yikun Chen , Xiao Zhong Zhu
IPC分类号： H01L29/06 , H01L29/78
CPC分类号： H01L29/0653 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/785 , H01L29/7854
摘要： A FINFET transistor structure includes a substrate including a fin structure. Two combined recesses embedded within the substrate, wherein each of the combined recesses includes a first recess extending in a vertical direction and a second recess extending in a lateral direction, the second recess has a protruding side extending to and under the fin structure. Two filling layers respectively fill in the combined recesses. A gate structure crosses the fin structure.
摘要翻译： FINFET晶体管结构包括包括鳍结构的衬底。嵌入在基板内的两个组合的凹槽，其中每个组合的凹槽包括沿垂直方向延伸的第一凹部和沿横向方向延伸的第二凹槽，第二凹部具有延伸到翅片结构下方和下方的突出侧。两个填充层分别填充组合的凹部。栅极结构穿过鳍结构。

7. 发明申请

US20170162450A1 SEMICONDUCTOR PROCESS 审中-公开
公开(公告)号：US20170162450A1
公开(公告)日：2017-06-08
申请号：US15435280
申请日：2017-02-16
申请人： UNITED MICROELECTRONICS CORP.
发明人： Duan Quan Liao , Yikun Chen , Ching-Hwa Tey , Xiao Zhong Zhu
IPC分类号： H01L21/8238 , H01L23/535 , H01L29/08 , H01L29/161 , H01L27/11 , H01L29/78 , H01L21/285 , H01L21/768 , H01L29/66 , H01L27/092 , H01L29/16
CPC分类号： H01L21/823871 , H01L21/28518 , H01L21/76805 , H01L21/76895 , H01L21/823814 , H01L21/823821 , H01L23/535 , H01L27/0924 , H01L27/1104 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/41791 , H01L29/517 , H01L29/66545 , H01L29/7848 , H01L29/785
摘要： A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided.

8. 发明授权

US09401280B2 Semiconductor process 有权
标题翻译：半导体工艺
公开(公告)号：US09401280B2
公开(公告)日：2016-07-26
申请号：US14288399
申请日：2014-05-28
申请人： UNITED MICROELECTRONICS CORP.
发明人： Duan Quan Liao , Wei Cheng , Yikun Chen , Ching Hwa Tey , Xiao Zhong Zhu
IPC分类号： H01L21/28 , H01L27/115
CPC分类号： H01L21/28273 , H01L27/11521 , H01L27/11534
摘要： A semiconductor process includes the following steps. A first gate is formed on a substrate, wherein the first gate includes a stacked gate on the substrate and a cap on the stacked gate. A spacer material is formed to conformally cover the first gate and the substrate. The spacer material is etched to form a spacer on a side of the first gate and a block on the other side of the first gate corresponding to the side. A material covers the substrate, the block, the first gate and the spacer, wherein the top surface of the material is a flat surface. The block, the spacer and the material are pulled down with the same pulling selectivity so that an assisting gate is formed from the block and a selective gate is formed from the spacer.
摘要翻译：半导体工艺包括以下步骤。第一栅极形成在衬底上，其中第一栅极包括衬底上的堆叠栅极和堆叠栅极上的帽。形成间隔物材料以保形地覆盖第一栅极和衬底。蚀刻间隔材料以在第一栅极的一侧上形成间隔物，并且在第一栅极的另一侧上对应于侧面的块。材料覆盖基板，块，第一栅极和间隔件，其中材料的顶表面是平坦的表面。块，间隔物和材料以相同的拉拔选择性被拉下，使得从块形成辅助栅极，并且由间隔物形成选择栅极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式