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1. 发明申请

US20210273076A1 METHOD OF FORMING GATE 有权
公开(公告)号：US20210273076A1
公开(公告)日：2021-09-02
申请号：US16802564
申请日：2020-02-27
申请人： UNITED MICROELECTRONICS CORP.
发明人： Yang-Ju Lu , Chun-Yi Wang , Fu-Shou Tsai , Yong-Yi Lin , Ching-Yang Chuang , Wen-Chin Lin , Hsin-Kuo Hsu
IPC分类号： H01L29/66 , H01L21/3105 , H01L21/02
摘要： A method of forming a gate includes the following steps. A gate structure is formed on a substrate. An etch stop layer is formed on the gate structure and the substrate. A dielectric layer is formed to cover the etch stop layer. The dielectric layer is planarized to form a planarized top surface of the dielectric layer and expose a portion of the etch stop layer on the gate structure. An oxygen containing treatment is performed to form an oxygen containing layer on the exposed etch stop layer. A deposition process is performed to form an oxide layer covering the planarized top surface of the dielectric layer and the oxygen containing layer.

2. 发明授权

US09478628B1 Metal gate forming process 有权
标题翻译：金属浇口成型工艺
公开(公告)号：US09478628B1
公开(公告)日：2016-10-25
申请号：US14853956
申请日：2015-09-14
申请人： UNITED MICROELECTRONICS CORP.
发明人： Kuo-Chih Lai , Nien-Ting HO , Chi-Mao Hsu , Ching-Yun Chang , Yen-Chen Chen , Yang-Ju Lu , Shih-Min Chou , Yun-Tzu Chang , Hsiang-Chieh Yen , Min-Chuan Tsai
IPC分类号： H01L21/4763 , H01L29/49 , H01L29/40 , H01L29/423 , H01L21/28
CPC分类号： H01L21/28088 , H01L29/66545
摘要： A metal gate forming process includes the following steps. A first metal layer is formed on a substrate by at least a first step followed by a second step, wherein the processing power of the second step is higher than the processing power of the first step.
摘要翻译：金属栅极形成工艺包括以下步骤。第一金属层通过至少第一步骤和第二步骤形成在衬底上，其中第二步骤的处理能力高于第一步骤的处理能力。

3. 发明申请

US20170148891A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
公开(公告)号：US20170148891A1
公开(公告)日：2017-05-25
申请号：US14951446
申请日：2015-11-24
申请人： UNITED MICROELECTRONICS CORP.
发明人： Kuo-Chih Lai , Yun-Tzu Chang , Wei-Ming Hsiao , Nien-Ting Ho , Shih-Min Chou , Yang-Ju Lu , Ching-Yun Chang , Yen-Chen Chen , Kuan-Chun Lin , Chi-Mao Hsu
IPC分类号： H01L29/51 , H01L29/49 , H01L29/40
CPC分类号： H01L29/513 , H01L21/823821 , H01L21/823842 , H01L21/845 , H01L27/1211 , H01L29/401 , H01L29/4966 , H01L29/517
摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

4. 发明授权

US11257711B1 Fabricating method of transistors without dishing occurred during CMP process 有权
公开(公告)号：US11257711B1
公开(公告)日：2022-02-22
申请号：US17023391
申请日：2020-09-17
申请人： UNITED MICROELECTRONICS CORP.
发明人： Fu-Shou Tsai , Yang-Ju Lu , Yong-Yi Lin , Yu-Lung Shih , Ching-Yang Chuang , Ji-Min Lin , Kun-Ju Li
IPC分类号： H01L21/768 , H01L21/8234 , H01L21/3105 , H01L21/311 , H01L21/02
摘要： A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.

5. 发明授权

US10340350B2 Semiconductor structure and manufacturing method thereof 有权
公开(公告)号：US10340350B2
公开(公告)日：2019-07-02
申请号：US16044581
申请日：2018-07-25
申请人： UNITED MICROELECTRONICS CORP.
发明人： Shih-Min Chou , Yun-Tzu Chang , Wei-Ning Chen , Wei-Ming Hsiao , Chia-Chang Hsu , Kuo-Chih Lai , Yang-Ju Lu , Yen-Chen Chen , Chun-Yao Yang
IPC分类号： H01L29/76 , H01L29/94 , H01L29/423 , H01L29/06 , H01L29/49 , H01L29/51 , H01L21/02 , H01L21/28 , H01L21/762 , H01L27/088 , H01L27/092 , H01L21/8238 , H01L21/3213 , H01L21/8234
摘要： A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.

6. 发明授权

US09728467B2 Method for modulating work function of semiconductor device having metal gate structure by gas treatment 有权
公开(公告)号：US09728467B2
公开(公告)日：2017-08-08
申请号：US14880693
申请日：2015-10-12
申请人： United Microelectronics Corp.
发明人： Yun-Tzu Chang , Shih-Min Chou , Kuo-Chih Lai , Ching-Yun Chang , Hsiang-Chieh Yen , Yen-Chen Chen , Yang-Ju Lu , Nien-Ting Ho , Chi-Mao Hsu
IPC分类号： H01L21/302 , H01L29/788 , H01L21/28 , H01L21/8238
CPC分类号： H01L21/823842
摘要： A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.

7. 发明申请

US20180261675A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20180261675A1
公开(公告)日：2018-09-13
申请号：US15453351
申请日：2017-03-08
申请人： UNITED MICROELECTRONICS CORP.
发明人： Shih-Min Chou , Yun-Tzu Chang , Wei-Ning Chen , Wei-Ming Hsiao , Chia-Chang Hsu , Kuo-Chih Lai , Yang-Ju Lu , Yen-Chen Chen , Chun-Yao Yang
IPC分类号： H01L29/423 , H01L29/06 , H01L29/49 , H01L29/51 , H01L21/02 , H01L21/28 , H01L21/762 , H01L27/088 , H01L27/092
摘要： A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.

8. 发明授权

US10074725B1 Semiconductor structure and manufacturing method thereof 有权
公开(公告)号：US10074725B1
公开(公告)日：2018-09-11
申请号：US15453351
申请日：2017-03-08
申请人： UNITED MICROELECTRONICS CORP.
发明人： Shih-Min Chou , Yun-Tzu Chang , Wei-Ning Chen , Wei-Ming Hsiao , Chia-Chang Hsu , Kuo-Chih Lai , Yang-Ju Lu , Yen-Chen Chen , Chun-Yao Yang
IPC分类号： H01L29/76 , H01L29/94 , H01L29/423 , H01L29/06 , H01L29/49 , H01L29/51 , H01L21/02 , H01L21/28 , H01L21/762 , H01L27/088 , H01L27/092 , H01L21/8238 , H01L21/8234
摘要： A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.

9. 发明授权

US09966425B1 Method for fabricating a MIM capacitor 有权
公开(公告)号：US09966425B1
公开(公告)日：2018-05-08
申请号：US15445953
申请日：2017-02-28
申请人： UNITED MICROELECTRONICS CORP.
发明人： Jen-Po Huang , Chin-Fu Lin , Bin-Siang Tsai , Xu Yang Shen , Seng Wah Liau , Yen-Chen Chen , Ko-Wei Lin , Chun-Ling Lin , Kuo-Chih Lai , Ai-Sen Liu , Chun-Yuan Wu , Yang-Ju Lu
IPC分类号： H01L21/8242 , H01L49/02
CPC分类号： H01L28/56 , H01L28/60
摘要： A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.

10. 发明申请

US20170076995A1 METHOD FOR MODULATING WORK FUNCTION OF SEMICONDUCTOR DEVICE HAVING METAL GATE STRUCTURE BY GAS TREATMENT 有权
标题翻译：用于调节具有气体处理的金属结构结构的半导体器件的工作功能的方法
公开(公告)号：US20170076995A1
公开(公告)日：2017-03-16
申请号：US14880693
申请日：2015-10-12
申请人： United Microelectronics Corp.
发明人： Yun-Tzu Chang , Shih-Min Chou , Kuo-Chih Lai , Ching-Yun Chang , Hsiang-Chieh Yen , Yen-Chen Chen , Yang-Ju Lu , Nien-Ting Ho , Chi-Mao Hsu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.
摘要翻译：提供了一种用于调制具有包括以下步骤的金属栅极结构的半导体器件的功函数的方法。在基板上设置具有相同结构的第一堆叠栅极结构和第二堆叠栅极结构。第一堆叠栅极结构和第二堆叠栅极结构分别包括第一类型的第一功函数金属层。形成图案化的硬掩模层。图案化的硬掩模层暴露第一堆叠栅极结构的第一功函数金属层并且覆盖第二堆叠栅极结构的第一功函数金属层。对由图案化的硬掩模层暴露的第一堆叠栅极结构的第一功函数金属层进行第一气体处理。在第一气体处理中使用的气体包括含氮气体或含氧气体。

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