专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US11069386B2 Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory 有权
公开(公告)号：US11069386B2
公开(公告)日：2021-07-20
申请号：US16869816
申请日：2020-05-08
申请人： Unity Semiconductor Corporation
发明人： Christophe Chevallier , Seow Fong Lim , Chang Hua Siau
IPC分类号： G11C7/00 , G11C7/22 , G11C5/02 , G11C11/21 , G11C13/00 , G11C8/10 , G11C8/12 , G11C7/04 , B82Y30/00
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

2. 发明授权

US10650870B2 Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory 有权
公开(公告)号：US10650870B2
公开(公告)日：2020-05-12
申请号：US16276333
申请日：2019-02-14
申请人： Unity Semiconductor Corporation
发明人： Christophe Chevallier , Seow Fong Lim , Chang Hua Siau
IPC分类号： G11C7/00 , G11C7/22 , G11C5/02 , G11C11/21 , G11C13/00 , G11C8/10 , G11C8/12 , G11C7/04 , B82Y30/00
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

3. 发明申请

US20190252011A1 CIRCUITS AND TECHNIQUES TO COMPENSATE MEMORY ACCESS SIGNALS FOR VARIATIONS OF PARAMETERS IN MULTIPLE LAYERS OF MEMORY 审中-公开
公开(公告)号：US20190252011A1
公开(公告)日：2019-08-15
申请号：US16276333
申请日：2019-02-14
申请人： Unity Semiconductor Corporation
发明人： Christophe Chevallier , Seow Fong Lim , Chang Hua Siau
IPC分类号： G11C7/22 , G11C8/12 , G11C8/10 , G11C13/00 , G11C5/02 , G11C11/21
CPC分类号： G11C7/22 , B82Y30/00 , G11C5/02 , G11C7/04 , G11C8/10 , G11C8/12 , G11C11/21 , G11C13/0021
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

4. 发明授权

US10210917B2 Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory 有权
公开(公告)号：US10210917B2
公开(公告)日：2019-02-19
申请号：US15868280
申请日：2018-01-11
申请人： Unity Semiconductor Corporation
发明人： Christophe Chevallier , Seow Fong Lim , Chang Hua Siau
IPC分类号： G11C7/00 , G11C7/22 , G11C5/02 , G11C11/21 , G11C13/00 , G11C8/10 , G11C8/12 , B82Y30/00 , G11C7/04
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

5. 发明申请

US20180342268A1 LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCESS MEMORY ELEMENTS IN CROSS-POINT ARRAYS 审中-公开
公开(公告)号：US20180342268A1
公开(公告)日：2018-11-29
申请号：US15984107
申请日：2018-05-18
申请人： Unity Semiconductor Corporation
发明人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson , Seow Fong Lim , Sri Rama Namala
IPC分类号： G11C5/02 , H01L45/00 , G11C13/00 , G11C8/00 , H01L21/82 , G11C11/00 , H01L27/24
摘要： Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

6. 发明授权

US09870809B2 Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory 有权
公开(公告)号：US09870809B2
公开(公告)日：2018-01-16
申请号：US15197482
申请日：2016-06-29
申请人： Unity Semiconductor Corporation
发明人： Christophe Chevallier , Seow Fong Lim , Chang Hua Siau
IPC分类号： G11C7/22 , G11C5/02 , G11C11/21 , G11C13/00 , G11C8/10 , G11C8/12 , B82Y30/00 , G11C7/04
CPC分类号： G11C7/22 , B82Y30/00 , G11C5/02 , G11C7/04 , G11C8/10 , G11C8/12 , G11C11/21 , G11C13/0021
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

7. 发明申请

US20160379692A1 CIRCUITS AND TECHNIQUES TO COMPENSATE MEMORY ACCESS SIGNALS FOR VARIATIONS OF PARAMETERS IN MULTIPLE LAYERS OF MEMORY 有权
公开(公告)号：US20160379692A1
公开(公告)日：2016-12-29
申请号：US15197482
申请日：2016-06-29
申请人： Unity Semiconductor Corporation
发明人： Christophe Chevallier , Seow Fong Lim , Chang Hua Siau
IPC分类号： G11C7/22 , G11C8/12 , G11C8/10
CPC分类号： G11C7/22 , B82Y30/00 , G11C5/02 , G11C7/04 , G11C8/10 , G11C8/12 , G11C11/21 , G11C13/0021
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

8. 发明授权

US09129668B2 Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory 有权
标题翻译：补偿存储器访问信号的电路和技术，用于在多层存储器中的参数变化
公开(公告)号：US09129668B2
公开(公告)日：2015-09-08
申请号：US14476632
申请日：2014-09-03
申请人： Unity Semiconductor Corporation
发明人： Christophe Chevallier , Seow Fong Lim , Chang Hua Siau
IPC分类号： G11C11/34 , G11C7/22 , G11C5/02 , G11C11/21 , G11C13/00 , B82Y30/00 , G11C7/04
CPC分类号： G11C7/22 , B82Y30/00 , G11C5/02 , G11C7/04 , G11C8/10 , G11C8/12 , G11C11/21 , G11C13/0021
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
摘要翻译：本发明的实施例一般涉及半导体和存储器技术，更具体地，涉及用于实现电路的系统，集成电路和方法，所述电路被配置为通过在存储器操作期间调整存取信号来补偿存储器层中的参数变化。在一些实施例中，存储器单元基于第三维存储器技术。在至少一些实施例中，集成电路包括多层存储器，包括半导体材料子层的层。集成电路还包括被配置为生成访问信号以便于访问操作的访问信号发生器，以及被配置为调整多层存储器中的每层的访问信号的特征调整器。

9. 发明申请

US20140369151A1 HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY 有权
标题翻译：用于跨点阵列的高电压开关电路
公开(公告)号：US20140369151A1
公开(公告)日：2014-12-18
申请号：US14312022
申请日：2014-06-23
申请人： Unity Semiconductor Corporation
发明人： Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C8/08 , G11C8/10
CPC分类号： G11C13/0023 , G11C8/08 , G11C8/10 , G11C13/0007 , G11C13/0028 , G11C2213/31 , G11C2213/71 , G11C2213/77 , H03K3/356104 , H03K19/018521
摘要： Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example.
摘要翻译：公开了用于产生用于对非易失性可重写存储器阵列执行数据操作的电压电平的电路。在一些实施例中，集成电路包括衬底和形成在衬底上的基底层，以包括被配置为在第一电压范围内操作的有源器件。此外，集成电路可以包括形成在基极层上方的交叉点存储器阵列，并且包括可重写的两端存储单元，其被配置为例如在大于第一电压范围的第二电压范围内操作。交叉点存储器阵列中的导电阵列线与基极层中的有源器件电耦合。集成电路还可以包括X线解码器和Y线解码器，其中包括在第一电压范围内工作的器件。有源器件可以包括其他有源电路，例如用于从存储器单元读取数据的感测放大器。

10. 发明授权

US08654565B2 Access signal adjustment circuits and methods for memory cells in a cross-point array 有权
标题翻译：交叉点阵列中存储单元的访问信号调整电路和方法
公开(公告)号：US08654565B2
公开(公告)日：2014-02-18
申请号：US13658697
申请日：2012-10-23
申请人： Unity Semiconductor Corporation
发明人： Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C11/00
CPC分类号： G11C13/0033 , G11C11/21 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.
摘要翻译：本发明的实施例一般涉及半导体和存储器技术，更具体地涉及系统，集成电路和方法，用于产生存取信号以促进存储器元件的按比例排列的存储器操作，诸如在形成的第三维存储器技术中实现的存储器直接位于包含数据访问电路的FEOL基板之上。在至少一些实施例中，非易失性存储器件可以包括具有布置在字线和位线子集之间的电阻性存储器元件的交叉点阵列和存取信号发生器。访问信号发生器可被配置为修改信号的大小以产生用于信号访问与字线和位线子集相关联的电阻性存储器元件的修改幅度。修改的幅度可以是交叉点阵列中的电阻性存储元件的位置的函数。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式