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1. 发明公开

US20240179886A1 MEMORY-ELEMENT-INCLUDING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20240179886A1
公开(公告)日：2024-05-30
申请号：US18517572
申请日：2023-11-22
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Nozomu HARADA , Masakazu KAKUMU , Koji SAKUI
IPC分类号： H10B12/00 , G11C11/405 , G11C11/4096
CPC分类号： H10B12/20 , G11C11/405 , G11C11/4096
摘要： In a memory cell including a first gate insulating layer 5 and a first gate conductor layer 6 surrounding a pillar-shaped P layer 3a standing on a P layer substrate 1, a second gate insulating layer 9 in contact with a P layer 3b in contact with an upper surface of the P layer 3a, and N+ layers 11a and 11b at both ends of the P layer 3b and a MOS transistor including a pillar-shaped P layer 3aa standing on a P layer substrate 1a connecting to the same P layer substrate 1, a third gate insulating layer 9a in contact with the P layer 3aa, a third gate conductor layer 10a, and N+ layers 11aa and 11ba at both ends of a P layer 3ba, bottom portions of the P layer 3b and the P layer 3ba are located at substantially the same position.

2. 发明公开

US20230420044A1 MEMORY APPARATUS USING SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：US20230420044A1
公开(公告)日：2023-12-28
申请号：US18231053
申请日：2023-08-07
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Koji SAKUI , Nozomu HARADA
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0038 , G11C13/0097
摘要： A memory apparatus includes a page including a plurality of memory cells arranged in a column on a substrate. Each of voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell included in the page is controlled to perform a page write operation of retaining holes, which have been formed through an impact ionization phenomenon or using a gate induced drain leakage current, in a semiconductor base material, or each of voltages applied to the first and second gate conductor layers, third and fourth gate conductor layers, and the first and second impurity layers is controlled to perform a page erase operation of removing the holes from the semiconductor base material, and further lowering a voltage of the semiconductor base material through capacitive coupling with the first gate conductor layer and the second gate conductor layer.

3. 发明公开

US20230317142A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
公开(公告)号：US20230317142A1
公开(公告)日：2023-10-05
申请号：US18194960
申请日：2023-04-03
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Masakazu KAKUMU , Koji SAKUI , Nozomu HARADA
IPC分类号： G11C11/409 , H10B12/00
CPC分类号： G11C11/409 , H10B12/20
摘要： A p layer is a semiconductor base material. An n+ layer is disposed on one extension side. An n+ layer is disposed on the opposite side in contact with the p layer. A gate insulating layer partially covers the p layer. A first gate conductor layer contacts the insulating layer. A second gate conductor layer is electrically separated from the first gate conductor layer. Memory operation is performed by applying voltage to each of the layers. In the operation, the quotient of the impurity concentration of a region and the gate capacitance of a MOS structure constituted by the layers per unit area is larger than the quotient of the impurity concentration of a region and the gate capacitance of a MOS structure constituted by the layers per unit area.

4. 发明公开

US20230186966A1 MEMORY DEVICE USING SEMICONDUCTOR ELEMENT 审中-公开
公开(公告)号：US20230186966A1
公开(公告)日：2023-06-15
申请号：US18077895
申请日：2022-12-08
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Riichiro SHIROTA , Koji SAKUI , Nozomu HARADA
IPC分类号： G11C11/404 , H10B12/00 , G11C11/406 , G11C11/4096
CPC分类号： G11C11/404 , H01L27/10802 , G11C11/406 , G11C11/4096
摘要： A memory device includes pages each composed of memory cells arrayed in columns on a substrate. A page write operation of retaining a hole group formed by impact ionization inside a channel semiconductor layer, and a page erase operation of discharging the hole group from the channel semiconductor layer are performed. A first impurity layer is connected to a source line, a second impurity layer to a bit line, a first gate conductor layer to a first selection gate line, a second gate conductor layer to a drive control line, a third gate conductor layer to a second selection gate line, and a bit line to a sense amplifier circuit. Page data of a memory cell group selected in at least one page is read to the bit line. Zero volts or less is applied to the drive control line of the memory cell connected to an unselected page.

5. 发明公开

US20230145678A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE 审中-公开
公开(公告)号：US20230145678A1
公开(公告)日：2023-05-11
申请号：US17981634
申请日：2022-11-07
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Riichiro SHIROTA , Nozomu HARADA , Koji SAKUI , Masakazu KAKUMU
IPC分类号： G11C11/4097 , H01L27/108 , G11C11/408
CPC分类号： G11C11/4097 , H01L27/10802 , G11C11/4085
摘要： A dynamic flash memory is formed by stacking, on a first impurity layer on a P-layer substrate, a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, a third material layer, and a fourth material layer, forming a first hole penetrating these layers on the P-layer substrate, forming a semiconductor pillar by embedding the first hole with a semiconductor, removing the first, second, and third material layers to form second, third, and fourth holes, by oxidizing an outermost surface of the semiconductor pillar exposing in the second, third, and fourth holes to form first, second, and third gate insulating layers, and forming first, second, and third gate conductor layers embedded in the second, third, and fourth holes.

6. 发明申请

US20230039991A1 MEMORY DEVICE USING SEMICONDUCTOR ELEMENT 有权
公开(公告)号：US20230039991A1
公开(公告)日：2023-02-09
申请号：US17878485
申请日：2022-08-01
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Masakazu KAKUMU , Koji SAKUI , Nozomu HARADA
IPC分类号： H01L27/108 , H01L29/78 , G11C11/4096 , G11C5/06 , H01L29/06
摘要： An n+ layer 3a connected to a source line SL at both ends, an n+ layer 3b connected to a bit line BL, a first gate insulating layer 4a formed on a semiconductor substrate 1 existing on an insulating film 2, a gate conductor layer 16a connected to a plate line PL, a gate insulating layer 4b formed on the semiconductor substrate, and a second gate conductor layer 5b connected to a word line WL and having a work function different from a work function of the gate conductor layer 16a are disposed on the semiconductor substrate, and data hold operation of holding, near a gate insulating film, holes generated by an impact ionization phenomenon or gate-induced drain leakage current inside a channel region 12 of the semiconductor substrate 1 and data erase operation of removing the holes from inside the substrate 1 and the channel region 12 are performed by controlling voltage applied to the source line SL, the plate line PL, the word line WL, and the bit line BL.

7. 发明申请

US20220415901A1 METHOD FOR MANUFACTURING MEMORY DEVICE USING SEMICONDUCTOR ELEMENT 有权
公开(公告)号：US20220415901A1
公开(公告)日：2022-12-29
申请号：US17846319
申请日：2022-06-22
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Nozomu HARADA , Koji SAKUI
IPC分类号： H01L27/108
摘要： Provided is a step of forming, on a P-layer substrate 20, an N+ layer 21A to be connected to a source line SL, Si pillars 25a to 25d, N+ layers 23A to 23D to be connected to bit lines BL1 and BL2, HfO2 layers 30a and 32 surrounding lower and upper portions of the Si pillars 25a to 25d, a TiN layer 31a to be connected to a plate line PL, and TiN layers 33a and 33b to be connected to word lines WL1 and WL2. P layers 27a to 27d are formed so as to surround the Si pillars 25a to 25d and so as to be deposited on them to form a plurality of dynamic flash memory cells arranged in rows and columns.

8. 发明申请

US20220406781A1 MEMORY DEVICE USING SEMICONDUCTOR ELEMENT 有权
公开(公告)号：US20220406781A1
公开(公告)日：2022-12-22
申请号：US17844935
申请日：2022-06-21
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Koji SAKUI , Nozomu HARADA
IPC分类号： H01L27/108
摘要： A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line. During a refresh operation, at least one of word lines is selected and a voltage of the channel semiconductor layer of the selected word line is returned to a voltage in a state in which a page is written by controlling voltages applied to the selected word line, the drive control line, the source line, and the bit line and thereby forming the positive hole groups by an impact ionization phenomenon in the channel semiconductor layer.

9. 发明申请

US20220367474A1 MEMORY DEVICE USING SEMICONDUCTOR ELEMENT 有权
公开(公告)号：US20220367474A1
公开(公告)日：2022-11-17
申请号：US17872310
申请日：2022-07-25
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Koji SAKUI , Nozomu HARADA
IPC分类号： H01L27/108 , G11C11/404 , G11C11/4091 , G11C11/4096
摘要： In a memory device, pages are arrayed in a column direction on a substrate, each page constituted by memory cells arrayed in row direction on a substrate. Each memory cell includes a zonal P layer. N+ layers continuous with a source line and a bit line respectively are on both sides of the P layer. Gate insulating layers surround part of the P layer continuous with the N+ layer and part of the P layer continuous with the N+ layer, respectively. One side surface of the gate insulating layer is covered with a gate conductor layer continuous with a first plate line, and the other side surface is covered with a gate conductor layer continuous with a second plate line. A gate conductor layer continuous with a word line surrounds the gate insulating layer.

10. 发明申请

US20220310608A1 MEMORY DEVICE USING SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING THE SAME 有权
公开(公告)号：US20220310608A1
公开(公告)日：2022-09-29
申请号：US17706071
申请日：2022-03-28
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Nozomu HARADA , Koji SAKUI
IPC分类号： H01L27/108
摘要： There are an N+ layer 3a connected to a source line SL and an N+ layer 3b connected to a bit line BL at both ends of a Si pillar 2 standing on a substrate 1 in a perpendicular direction, a P+ layer 8 connected to the N+ layer 3b, a first gate insulating layer 4a surrounding the Si pillar 2, a first gate conductor layer 5a surrounding the first gate insulating layer 4a and connected to a plate line PL, and a second gate conductor layer 5b surrounding a gate HfO2 layer 4b surrounding the Si pillar 2 and connected to a word line WL. The voltages applied to the source line SL, the plate line PL, the word line WL, and the bit line BL are controlled to perform a data hold operation of holding a group of holes generated by an impact ion phenomenon or a gate-induced drain leakage current inside a channel region 7 of the Si pillar 2 and a data erase operation of removing the group of holes from the channel region 7.

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