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    • 1. 发明授权
    • Piezoelectric acceleration timer
    • 压电加速定时器
    • US09001626B1
    • 2015-04-07
    • US13046121
    • 2011-03-11
    • Vadim OlenAnders P. WalkerAdrian A. HillMichael C. Meholensky
    • Vadim OlenAnders P. WalkerAdrian A. HillMichael C. Meholensky
    • G04F8/00G04F8/02
    • G04F8/02G04F8/006G04F10/00
    • A timer for measuring a time lapsed during an acceleration is disclosed. The timer may include a piezoelectric sensor, an energy storage device and a measurement module. The piezoelectric sensor includes a piezoelectric material for generating an electric potential in response to the acceleration. The energy storage device is electrically coupled to the piezoelectric sensor and is configured for receiving the electric potential generated by the piezoelectric sensor. The measurement module is electrically coupled to the energy storage device. The measurement module measures the electric potential received at the energy storage device and determines the time lapsed during the acceleration based on the electric potential received at the energy storage device.
    • 公开了一种用于测量加速期间经过的时间的定时器。 定时器可以包括压电传感器,能量存储装置和测量模块。 压电传感器包括用于响应于加速度产生电位的压电材料。 能量存储装置电耦合到压电传感器并且被配置为接收由压电传感器产生的电位。 测量模块电耦合到能量存储装置。 测量模块测量在能量存储装置处接收的电位,并且基于在能量存储装置处接收的电位来确定加速期间所经过的时间。
    • 6. 发明授权
    • Stiffened backside fabrication for microwave radio frequency wafers
    • 加强微波射频晶片的背面制造
    • US06884717B1
    • 2005-04-26
    • US10034723
    • 2002-01-03
    • Gregory C. DesalvoTony K. QuachJohn L. EbelAnders P. WalkerPaul D. Cassity
    • Gregory C. DesalvoTony K. QuachJohn L. EbelAnders P. WalkerPaul D. Cassity
    • H01L21/306H01L21/308H01L21/44H01L21/768H01L21/78H01L23/66
    • H01L21/78H01L21/306H01L21/3083H01L21/76898H01L23/4824H01L23/66H01L2924/0002H01L2924/00
    • An etching based semiconductor wafer thinning arrangement usable as an improved alternative to the usual grinding and polishing wafer thinning. The thinned wafer includes a structurally enhancing wafer backside grid array of original wafer thickness semiconductor material with grid cells surrounding individual thinned wafer areas and serving to improve the strength and physical rigidity characteristics of the thinned wafer. Preferably this grid array is supplemented with an additional, wafer periphery-located, backside ring of semiconductor material also of original wafer thickness. Ability to avoid a wafer front side mounting during thinning accomplishment, fast etching, reduced wafer breakage, enhanced wafer strength and improved wafer handling achieved with the disclosed thinning arrangement all contribute to achieved advantages over conventional wafer thinning. Gallium arsenide or other semiconductor materials are contemplated along with use in radio frequency or other integrated circuit devices of either the single transistor or complete integrated circuit components types.
    • 基于蚀刻的半导体晶片薄化布置可用作通常的研磨和抛光晶片薄化的改进的替代。 薄化晶片包括结构上增强的原始晶片厚度半导体材料的晶片背面格栅阵列,其具有围绕各个薄化晶片区域的栅格单元,并且用于提高薄晶片的强度和物理刚度特性。 优选地,该栅格阵列补充有另外的晶片周边位于的也是原始晶片厚度的半导体材料的背面环。 通过所公开的稀化装置实现的减薄完成,快速蚀刻,减少的晶片断裂,增强的晶片强度以及改进的晶片处理,能够避免晶片正面安装,这都有助于实现优于常规晶片薄化的优点。 考虑砷化镓或其他半导体材料,以及在单晶体管或完整集成电路组件类型的射频或其他集成电路器件中的使用。