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1. 发明申请

US20110063022A1 OPTIMIZING POWER CONSUMPTION OF A DIGITAL CIRCUIT 有权
标题翻译：优化数字电路的功耗
公开(公告)号：US20110063022A1
公开(公告)日：2011-03-17
申请号：US12865860
申请日：2009-01-30
申请人： Van Assche Tom , Van Straaten Bram , Janssens Mark
发明人： Van Assche Tom , Van Straaten Bram , Janssens Mark
IPC分类号： G05F1/10
CPC分类号： H03L7/00 , G06F1/3203 , G06F1/324 , G06F1/3296 , H04R2460/03 , Y02D10/126 , Y02D10/172
摘要： A method is provided for optimizing power consumption of a digital circuit which provides operational functionality based upon operating demands. The digital circuit is subject to a supply voltage level and a clock frequency. The method includes determining an acceptable delay value, from a plurality of predetermined acceptable delay values, for the digital circuit based upon current operating demands and the clock frequency. The supply voltage level and the clock frequency are applied to a delay monitor circuit. The delay experienced by the delay monitoring circuit is measured. The measured delay is compared with the determined acceptable delay value. Based on the outcome of the comparing step, the supply voltage level applied to the digital circuit is selectively adjusted. An arrangement for implementing the method is also provided.
摘要翻译：提供一种用于优化基于操作需求提供操作功能的数字电路的功率消耗的方法。数字电路受到电源电压电平和时钟频率的影响。该方法包括基于当前的操作需求和时钟频率，从数个电路的多个预定的可接受的延迟值中确定可接受的延迟值。电源电压电平和时钟频率被施加到延迟监视电路。测量延迟监测电路所经历的延迟。将测量的延迟与所确定的可接受的延迟值进行比较。基于比较步骤的结果，选择性地调整施加到数字电路的电源电压。还提供了一种用于实现该方法的装置。

2. 发明授权

US09026821B2 Optimizing power consumption of a digital circuit 有权
标题翻译：优化数字电路的功耗
公开(公告)号：US09026821B2
公开(公告)日：2015-05-05
申请号：US12865860
申请日：2009-01-30
申请人： Van Assche Tom , Van Straaten Bram , Janssens Mark
发明人： Van Assche Tom , Van Straaten Bram , Janssens Mark
IPC分类号： G06F1/32 , H03L7/00
CPC分类号： H03L7/00 , G06F1/3203 , G06F1/324 , G06F1/3296 , H04R2460/03 , Y02D10/126 , Y02D10/172
摘要： A method is provided for optimizing power consumption of a digital circuit which provides operational functionality based upon operating demands. The digital circuit is subject to a supply voltage level and a clock frequency. The method includes determining an acceptable delay value, from a plurality of predetermined acceptable delay values, for the digital circuit based upon current operating demands and the clock frequency. The supply voltage level and the clock frequency are applied to a delay monitor circuit. The delay experienced by the delay monitoring circuit is measured. The measured delay is compared with the determined acceptable delay value. Based on the outcome of the comparing step, the supply voltage level applied to the digital circuit is selectively adjusted. An arrangement for implementing the method is also provided.
摘要翻译：提供一种用于优化基于操作需求提供操作功能的数字电路的功率消耗的方法。数字电路受到电源电压电平和时钟频率的影响。该方法包括基于当前的操作需求和时钟频率，从数个电路的多个预定的可接受的延迟值中确定可接受的延迟值。电源电压电平和时钟频率被施加到延迟监视电路。测量延迟监测电路所经历的延迟。将测量的延迟与所确定的可接受的延迟值进行比较。基于比较步骤的结果，选择性地调整施加到数字电路的电源电压。还提供了一种用于实现该方法的装置。

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