专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08165111B2 Telecommunication and computing platforms with serial packet switched integrated memory access technology 有权
标题翻译：具有串行分组交换集成存储器访问技术的电信和计算平台
公开(公告)号：US08165111B2
公开(公告)日：2012-04-24
申请号：US11828329
申请日：2007-07-25
申请人： Viswa Nath Sharma , Barton W. Stuck , Ching-Tai Hu , Yi-chang Chou , William Chu
发明人： Viswa Nath Sharma , Barton W. Stuck , Ching-Tai Hu , Yi-chang Chou , William Chu
IPC分类号： H04L12/50
CPC分类号： G06F13/4063
摘要： A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.
摘要翻译：计算和通信架构在包装布置中的电路卡之间使用基于串行协议的交换结构。在一个实施例中，在封装装置中连接到基于串行协议的交换结构的每个电路卡设置有协议处理器，其使得所有电路卡能够以线速度有效地提供基于分组的串行自定时通信。结果，不需要以分层方式布置电路卡，以便解决交换机阻塞和相关业务拥塞问题的问题，否则将限制基于串行协议的背板布置用于容纳电路卡的实现。

2. 发明授权

US09323708B2 Protocol translation method and bridge device for switched telecommunication and computing platforms 有权
标题翻译：交换电信和计算平台的协议翻译方法和桥接设备
公开(公告)号：US09323708B2
公开(公告)日：2016-04-26
申请号：US13421548
申请日：2012-03-15
申请人： Viswa Nath Sharma , Barton W. Stuck , Ching-Tai Hu , Yi-chang Chou , William Chu
发明人： Viswa Nath Sharma , Barton W. Stuck , Ching-Tai Hu , Yi-chang Chou , William Chu
IPC分类号： H04L12/28 , G06F13/40
CPC分类号： G06F13/4063
摘要： A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.
摘要翻译：计算和通信架构在包装布置中的电路卡之间使用基于串行协议的交换结构。在一个实施例中，在封装装置中连接到基于串行协议的交换结构的每个电路卡设置有协议处理器，其使得所有电路卡能够以线速度有效地提供基于分组的串行自定时通信。结果，不需要以分层方式布置电路卡，以便解决交换机阻塞和相关业务拥塞问题的问题，否则将限制基于串行协议的背板布置用于容纳电路卡的实现。

3. 发明授权

US08787364B2 Serial memory and IO access architecture and system for switched telecommunication and computing platforms 有权
标题翻译：用于交换电信和计算平台的串行存储器和IO接入架构和系统
公开(公告)号：US08787364B2
公开(公告)日：2014-07-22
申请号：US13421826
申请日：2012-03-15
申请人： Viswa Nath Sharma , Barton W. Stuck , Ching-Tai Hu , Yi-chang Chou , William Chu
发明人： Viswa Nath Sharma , Barton W. Stuck , Ching-Tai Hu , Yi-chang Chou , William Chu
IPC分类号： H04L12/50
CPC分类号： G06F13/4063
摘要： A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.
摘要翻译：计算和通信架构在包装布置中的电路卡之间使用基于串行协议的交换结构。在一个实施例中，在封装装置中连接到基于串行协议的交换结构的每个电路卡设置有协议处理器，其使得所有电路卡能够以线速度有效地提供基于分组的串行自定时通信。结果，不需要以分层方式布置电路卡，以便解决交换机阻塞和相关业务拥塞问题的问题，否则将限制基于串行协议的背板布置用于容纳电路卡的实现。

4. 发明授权

US08116309B2 Enhanced Ethernet protocol for shortened data frames within a constrained neighborhood based on unique ID 有权
标题翻译：增强型以太网协议，用于基于唯一ID缩短约束邻域内的数据帧
公开(公告)号：US08116309B2
公开(公告)日：2012-02-14
申请号：US11838198
申请日：2007-08-13
申请人： Viswa Nath Sharma
发明人： Viswa Nath Sharma
IPC分类号： H04L12/56
CPC分类号： H04L12/66
摘要： An enhanced Ethernet protocol for computing and telecommunication supports a shortened frame size for communicating data payloads among selected devices within a constrained neighborhood based on a unique identification.
摘要翻译：用于计算和通信的增强型以太网协议支持缩短的帧大小，用于基于唯一标识在受限邻域内的选定设备之间传送数据有效载荷。

5. 发明授权

US08234483B2 Memory units with packet processor for decapsulating read write access from and encapsulating response to external devices via serial packet switched protocol interface 有权
标题翻译：具有分组处理器的存储单元，用于通过串行分组交换协议接口解封装读写访问和封装对外部设备的响应
公开(公告)号：US08234483B2
公开(公告)日：2012-07-31
申请号：US12910867
申请日：2010-10-25
申请人： Viswa Nath Sharma
发明人： Viswa Nath Sharma
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/382 , G06F13/4282 , G06F15/16 , H04L12/4625 , H04L12/56
摘要： A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.
摘要翻译：提供了一种计算和通信芯片架构，其中处理器访问存储器芯片的接口被实现为作为每个芯片的一部分的高速分组交换串行接口。在一个实施例中，通过集成为芯片的一部分的协议处理器提供的千兆位以太网接口来实现接口。协议处理器将存储器地址和控制信息（如读取，写入，连续字节数等）封装为用于处理器和位于同一主板上的存储器芯片之间或甚至在不同电路卡上的通信的以太网分组。在一个实施例中，通过在受约束的邻域内使用具有缩短的数据帧的增强型以太网协议和/或通过利用比特流交换机来进一步减少以太网协议头上的通信，其中可以在包括的元素之间建立直接连接路径计算或通信架构。

6. 发明授权

US10965208B2 System and method for a multi purpose bidirectional power converter 有权
公开(公告)号：US10965208B2
公开(公告)日：2021-03-30
申请号：US15659669
申请日：2017-07-26
申请人： Viswa Nath Sharma
发明人： Viswa Nath Sharma
IPC分类号： H02M1/10 , H02M3/335 , H02M5/22 , H02M7/48 , H02M7/797
摘要： The present invention is directed to Bidirectional Multimode Power Converter which employs a high frequency dynamically varying amplitude modulation and voltage steering-method to convert the source AC or DC voltages to output AC or DC voltages with programmable output voltage levels, output voltage frequency and duration. The Bidirectional Multimode Power Converters of the present invention support: inrush current control, turning off the idle converter, line voltage brown out protection, soft start, high pre-charge voltage generation, soft shut down of converter, dimming operation, programmable time of the day operation and operation for specified duration of time. The Bidirectional Multimode Power Converters of the present invention support coupling of multiple power sources for bidirectional power conversion.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式