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1. 发明授权

US09384389B1 Detecting errors in recognized text 有权
标题翻译：检测识别文本中的错误
公开(公告)号：US09384389B1
公开(公告)日：2016-07-05
申请号：US13612273
申请日：2012-09-12
申请人： Viswanath Sankaranarayanan , Sridhar Jayaraman
发明人： Viswanath Sankaranarayanan , Sridhar Jayaraman
IPC分类号： G06K9/00
CPC分类号： G06K9/00456 , G06K9/03 , G06K9/72 , G06K2209/01
摘要： Some examples include detecting errors in text that has been recognized using automated text recognition technology. For instance, errors in the recognized text may be detected based on glyph image similarity and the use of a language model, dictionary information, or the like. Some implementations may group together glyphs based on association of the glyphs with the same glyph identifier and a similarity of the appearance of the glyphs. Furthermore, the words associated with each glyph may be checked against a language model, such as to check a spelling or other validity of the words, and a score may be assigned to each group of glyphs based on the validity of the words corresponding to the glyphs in that group. Groups that have a score that fails to meet a threshold may be reviewed by a person or may undergo automated correction techniques.
摘要翻译：一些例子包括检测已使用自动文本识别技术识别的文本中的错误。例如，可以基于字形图像相似度和语言模型，字典信息等的使用来检测识别的文本中的错误。一些实现可以基于字形与相同字形标识符的关联以及字形外观的相似性将字形组合在一起。此外，可以针对语言模型检查与每个字形相关联的单词，例如检查单词的拼写或其他有效性，并且可以基于对应于单词的单词的有效性将分数分配给每组字形该组中的字形。具有不符合阈值的分数的组可以由人员进行评估，或者可以进行自动校正技术。

2. 发明申请

US20070022342A1 Parallel test mode for multi-core processors 有权
标题翻译：多核处理器的并行测试模式
公开(公告)号：US20070022342A1
公开(公告)日：2007-01-25
申请号：US11174198
申请日：2005-06-30
申请人： Silvio Picano , Sridhar Jayaraman , Peter DesRosier , James Chung
发明人： Silvio Picano , Sridhar Jayaraman , Peter DesRosier , James Chung
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/318552 , G01R31/318563
摘要： An embodiment of the present invention is a technique to provide a parallel test mode for multi-core processors. A test access port (TAP) in a first processor core generates a first test data output (TDO) from a first test data input (TDI) or a first delayed TDI according to a TDO select bit. The first delayed TDI is clocked by a test clock (TCK). The first processor core has a first core circuit. The TAP generates a phase select word. A clock generator generates a clock signal synchronized with the TCK and has a low phase and a high phase. A first enable circuit enables first core data from the first core circuit in one of the low and high phases of the clock signal according to the phase select word.
摘要翻译：本发明的实施例是提供用于多核处理器的并行测试模式的技术。第一处理器核心中的测试访问端口（TAP）根据TDO选择位从第一测试数据输入（TDI）或第一延迟TDI产生第一测试数据输出（TDO）。第一个延迟TDI由测试时钟（TCK）计时。第一个处理器内核具有第一个核心电路。 TAP产生相位选择字。时钟发生器产生与TCK同步的时钟信号，具有低相位和高相位。第一使能电路根据相位选择字使得来自第一核心电路的第一核心数据在时钟信号的低相位和高相位之一中。

3. 发明授权

US07475309B2 Parallel test mode for multi-core processors 有权
标题翻译：多核处理器的并行测试模式
公开(公告)号：US07475309B2
公开(公告)日：2009-01-06
申请号：US11174198
申请日：2005-06-30
申请人： Silvio Picano , Sridhar Jayaraman , Peter DesRosier , James Chung
发明人： Silvio Picano , Sridhar Jayaraman , Peter DesRosier , James Chung
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/318552 , G01R31/318563
摘要： An embodiment of the present invention is a technique to provide a parallel test mode for multi-core processors. A test access port (TAP) in a first processor core generates a first test data output (TDO) from a first test data input (TDI) or a first delayed TDI according to a TDO select bit. The first delayed TDI is clocked by a test clock (TCK). The first processor core has a first core circuit. The TAP generates a phase select word. A clock generator generates a clock signal synchronized with the TCK and has a low phase and a high phase. A first enable circuit enables first core data from the first core circuit in one of the low and high phases of the clock signal according to the phase select word.
摘要翻译：本发明的实施例是提供用于多核处理器的并行测试模式的技术。第一处理器核心中的测试访问端口（TAP）根据TDO选择位从第一测试数据输入（TDI）或第一延迟TDI产生第一测试数据输出（TDO）。第一个延迟TDI由测试时钟（TCK）计时。第一个处理器内核具有第一个核心电路。 TAP产生相位选择字。时钟发生器产生与TCK同步的时钟信号，具有低相位和高相位。第一使能电路根据相位选择字使得来自第一核心电路的第一核心数据在时钟信号的低相位和高相位之一中。

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