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    • 3. 发明申请
    • SIGNAL SPLITTER
    • 信号分离器
    • US20090206906A1
    • 2009-08-20
    • US11575489
    • 2005-09-08
    • Thibault Philippe Paul KervaonSebastien Amiot
    • Thibault Philippe Paul KervaonSebastien Amiot
    • H03L5/00
    • H03G1/0029
    • A controllable-gain circuit (TI, Rt, TS1, . . . , TS4) provides a first and a second pair of complementary gain-controlled signals (Ip1, Ip3; Ip2, Ip4) in response to an input signal (RFI). In each pair, one gain-controlled signal (Ip1, Ip2) is the input signal amplified with a gain G comprised in a range between a minimum gain Gmin and a maximum gain Gmax. The other gain-controlled signal (Ip3, Ip4) is the input signal amplified with complementary gain Gmax-G. A fixed-gain output circuit (Rfg, Nfg) makes a weighed sum (Ip1*Rfg+Ip3*Rfg) of one and the other gain-controlled signal in the first pair of complementary gain-controlled signals. The respective weighing factors for one and the other gain-controlled signal are substantially similar (Rfg). A controllable-gain output circuit (Rlg, Rhg, Nlg, Nhg) makes a weighed sum (Ip2*Rlg+Ip4*(Rlg+Rhg)) of one and the other gaincontrolled signal in the second pair of complementary gain-controlled signals. The respective weighing factors for one and the other gain-controlled signal are substantially different (Rlg, Rlg+Rhg).
    • 响应于输入信号(RFI),可控增益电路(TI,Rt,TS1,...,TS4)提供第一和第二对互补增益控制信号(Ip1,Ip3; Ip2,Ip4)。 在每对中,一个增益控制信号(Ip1,Ip2)是以包括在最小增益Gmin和最大增益Gmax之间的范围内的增益G放大的输入信号。 其他增益控制信号(Ip3,Ip4)是用互补增益Gmax-G放大的输入信号。 固定增益输出电路(Rfg,Nfg)在第一对互补增益控制信号中产生一个和另一个增益控制信号的加权和(Ip1 * Rfg + Ip3 * Rfg)。 一个和另一个增益控制信号的各个称重因子基本相似(Rfg)。 可控增益输出电路(Rlg,Rhg,Nlg,Nhg)在第二对互补增益控制信号中产生一个和另一个增益控制信号的加权和(Ip2 * Rlg + Ip4 *(Rlg + Rhg))。 一个和另一个增益控制信号的各个称重因子基本上不同(R1g,Rlg + Rhg)。
    • 7. 发明申请
    • HARMONIC REJECTION MIXER UNIT AND METHOD FOR PERFORMING A HARMONIC REJECTION MIXING
    • 谐波抑制混合器单元和执行谐波抑制混合的方法
    • US20100283526A1
    • 2010-11-11
    • US12671734
    • 2008-07-30
    • Jan Van SinderenSebastien AmiotLeonardus H. M. Hessen
    • Jan Van SinderenSebastien AmiotLeonardus H. M. Hessen
    • G06G7/14G06G7/12
    • H03D7/1441H03D7/145H03D7/1458H03D7/1466H03D7/1483H03D7/165H03D7/166H03D7/18H03D2200/0086
    • A harmonic rejection mixer unit is provided which comprises an input (RF), at least one harmonic rejection unit (HRU) with at least two transistor units (T3a, T3b; T4a, T4b) for multiplying an input signal from the input (RF) with a multiplication signal (ELO). The harmonic rejection mixer unit furthermore comprises a transistor control signal generating unit (GGU) for generating transistor control signals (GS1-GS4) for the at least two transistor units (T3a, T3b; T4a, T4b) of the at least one harmonic rejection unit (HRU) by deriving the transistor control signals (GS1-GS4) from a local oscillator signal (LO). The transistor control signals (GS3, GS4) for the at least two transistor units (T3a, T3b; T4a, T4b) are generated with a duty cycle of
    • 提供了一种谐波抑制混频器单元,其包括输入(RF),至少一个具有至少两个晶体管单元(T3a,T3b; T4a,T4b)的谐波抑制单元(HRU),用于将来自输入(RF) 具有乘法信号(ELO)。 谐波抑制混频器单元还包括晶体管控制信号生成单元(GGU),用于产生用于至少一个谐波抑制单元的至少两个晶体管单元(T3a,T3b; T4a,T4b)的晶体管控制信号(GS1-GS4) (HR1)通过从本地振荡器信号(LO)导出晶体管控制信号(GS1-GS4)。 以占空比<50%生成用于至少两个晶体管单元(T3a,T3b; T4a,T4b)的晶体管控制信号(GS3,GS4),并产生使得乘法信号ELO的形状得以实现 通过来自晶体管单元(T3a,T3b; T4a,T4b)的输出信号的构造求和。 产生晶体管控制信号(GS1-GS4),使得只执行来自具有相同符号或零的晶体管单元的输出信号的总和。
    • 8. 发明授权
    • Signal splitter
    • 信号分路器
    • US07816991B2
    • 2010-10-19
    • US11575489
    • 2005-09-08
    • Thibault Philippe Paul KervaonSebastien Amiot
    • Thibault Philippe Paul KervaonSebastien Amiot
    • H03G3/30
    • H03G1/0029
    • A controllable-gain circuit (TI, Rt, TS1, . . . , TS4) provides a first and a second pair of complementary gain-controlled signals (Ip1, Ip3; Ip2, Ip4) in response to an input signal (RFI). In each pair, one gain-controlled signal (Ip1, Ip2) is the input signal amplified with a gain G comprised in a range between a minimum gain Gmin and a maximum gain Gmax. The other gain-controlled signal (Ip3, Ip4) is the input signal amplified with complementary gain Gmax-G. A fixed-gain output circuit (Rfg, Nfg) makes a weighed sum (Ip1*Rfg+Ip3*Rfg) of one and the other gain-controlled signal in the first pair of complementary gain-controlled signals. The respective weighing factors for one and the other gain-controlled signal are substantially similar (Rfg). A controllable-gain output circuit (Rlg, Rhg, Nlg, Nhg) makes a weighed sum (Ip2*Rlg+Ip4*(Rlg+Rhg)) of one and the other gaincontrolled signal in the second pair of complementary gain-controlled signals. The respective weighing factors for one and the other gain-controlled signal are substantially different (Rlg, Rlg+Rhg).
    • 响应于输入信号(RFI),可控增益电路(TI,Rt,TS1,...,TS4)提供第一和第二对互补增益控制信号(Ip1,Ip3; Ip2,Ip4)。 在每对中,一个增益控制信号(Ip1,Ip2)是以包括在最小增益Gmin和最大增益Gmax之间的范围内的增益G放大的输入信号。 其他增益控制信号(Ip3,Ip4)是用互补增益Gmax-G放大的输入信号。 固定增益输出电路(Rfg,Nfg)在第一对互补增益控制信号中产生一个和另一个增益控制信号的加权和(Ip1 * Rfg + Ip3 * Rfg)。 一个和另一个增益控制信号的各个称重因子基本相似(Rfg)。 可控增益输出电路(Rlg,Rhg,Nlg,Nhg)在第二对互补增益控制信号中产生一个和另一个增益控制信号的加权和(Ip2 * Rlg + Ip4 *(Rlg + Rhg))。 一个和另一个增益控制信号的各个称重因子基本上不同(R1g,Rlg + Rhg)。
    • 9. 发明授权
    • Harmonic rejection mixer unit and method for performing a harmonic rejection mixing
    • 谐波抑制混频器单元和执行谐波抑制混频的方法
    • US08280333B2
    • 2012-10-02
    • US12671734
    • 2008-07-30
    • Jan Van SinderenSebastien AmiotLeonardus H. M. Hesen
    • Jan Van SinderenSebastien AmiotLeonardus H. M. Hesen
    • H04B1/10H04K3/00
    • H03D7/1441H03D7/145H03D7/1458H03D7/1466H03D7/1483H03D7/165H03D7/166H03D7/18H03D2200/0086
    • A harmonic rejection mixer unit is provided which comprises an input (RF), at least one harmonic rejection unit (HRU) with at least two transistor units (T3a, T3b; T4a, T4b) for multiplying an input signal from the input (RF) with a multiplication signal (ELO). The harmonic rejection mixer unit furthermore comprises a transistor control signal generating unit (GGU) for generating transistor control signals (GS1-GS4) for the at least two transistor units (T3a, T3b; T4a, T4b) of the at least one harmonic rejection unit (HRU) by deriving the transistor control signals (GS1-GS4) from a local oscillator signal (LO). The transistor control signals (GS3, GS4) for the at least two transistor units (T3a, T3b; T4a, T4b) are generated with a duty cycle of
    • 提供了一种谐波抑制混频器单元,其包括输入(RF),至少一个具有至少两个晶体管单元(T3a,T3b; T4a,T4b)的谐波抑制单元(HRU),用于将来自输入(RF) 具有乘法信号(ELO)。 谐波抑制混频器单元还包括晶体管控制信号生成单元(GGU),用于产生用于至少一个谐波抑制单元的至少两个晶体管单元(T3a,T3b; T4a,T4b)的晶体管控制信号(GS1-GS4) (HR1)通过从本地振荡器信号(LO)导出晶体管控制信号(GS1-GS4)。 以占空比<50%生成用于至少两个晶体管单元(T3a,T3b; T4a,T4b)的晶体管控制信号(GS3,GS4),并产生使得乘法信号ELO的形状得以实现 通过来自晶体管单元(T3a,T3b; T4a,T4b)的输出信号的构造求和。 产生晶体管控制信号(GS1-GS4),使得只执行来自具有相同符号或零的晶体管单元的输出信号的总和。